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From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <p.yadav@ti.com>, <michael@walle.cc>, <broonie@kernel.org>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>, <nicolas.ferre@microchip.com>,
	Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH v2 3/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
Date: Fri, 11 Mar 2022 10:01:44 +0200	[thread overview]
Message-ID: <20220311080147.453483-4-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com>

Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/sfdp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index f5432cbd3daf..e049851a57a7 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -579,6 +579,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable)
 #define BFPT_DWORD18_CMD_EXT_INV		(0x1UL << 29) /* Invert */
 #define BFPT_DWORD18_CMD_EXT_RES		(0x2UL << 29) /* Reserved */
 #define BFPT_DWORD18_CMD_EXT_16B		(0x3UL << 29) /* 16-bit opcode */
+#define BFPT_DWORD18_BYTE_ORDER_SWAPPED		BIT(31)
 
 /**
  * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
@@ -832,6 +833,9 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 		return -EOPNOTSUPP;
 	}
 
+	if (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED)
+		nor->flags |= SNOR_F_DTR_SWAB16;
+
 	return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt);
 }
 
-- 
2.25.1


  parent reply	other threads:[~2022-03-11  8:02 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-11  8:01 [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Tudor Ambarus
2022-03-11  8:01 ` [PATCH v2 1/6] spi: " Tudor Ambarus
2022-03-11  8:01 ` [PATCH v2 2/6] mtd: spi-nor: core: " Tudor Ambarus
2022-03-11  8:01 ` Tudor Ambarus [this message]
2022-03-11  8:01 ` [PATCH v2 4/6] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Tudor Ambarus
2022-03-11  8:01 ` [PATCH v2 5/6] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Tudor Ambarus
2022-03-11  8:01 ` [PATCH v2 6/6] mtd: spi-nor: macronix: Add support for mx66lm1g45g Tudor Ambarus
2022-03-15  6:08 ` [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Vignesh Raghavendra
2022-03-15  6:58   ` Tudor.Ambarus
2022-03-16  7:08     ` Vignesh Raghavendra
2022-03-16  8:39       ` Michael Walle
2022-03-15  7:19   ` Michael Walle
2022-03-16  7:05     ` Vignesh Raghavendra
2022-03-16  7:57       ` Tudor.Ambarus
2022-03-16 13:55       ` David Laight
2022-03-17  9:40         ` Michael Walle
2022-03-17 10:14           ` David Laight
2022-03-17 10:23             ` Vignesh Raghavendra
2022-03-17 11:10               ` David Laight
2022-03-17 16:49                 ` Vignesh Raghavendra

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