From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <p.yadav@ti.com>, <michael@walle.cc>, <broonie@kernel.org>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <nicolas.ferre@microchip.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH v2 4/6] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag
Date: Fri, 11 Mar 2022 10:01:45 +0200 [thread overview]
Message-ID: <20220311080147.453483-5-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com>
Introduce SPI_NOR_DTR_BSWAP16 flag for flashes that don't define the
mandatory BFPT table. When set it indicates that the byte order of 16-bit
words is swapped when read in 8D-8D-8D mode compared to 1-1-1 mode.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
---
drivers/mtd/spi-nor/core.c | 5 ++++-
drivers/mtd/spi-nor/core.h | 6 +++++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index a69c2813f6fc..d7eebbd01122 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2298,7 +2298,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *map = ¶ms->erase_map;
- const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
+ const u16 no_sfdp_flags = nor->info->no_sfdp_flags;
u8 i, erase_mask;
if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
@@ -2339,6 +2339,9 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
}
+ if (no_sfdp_flags & SPI_NOR_DTR_SWAB16)
+ nor->flags |= SNOR_F_DTR_SWAB16;
+
/*
* Sector Erase settings. Sort Erase Types in ascending order, with the
* smallest erase size starting at BIT(0).
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 0dcbc7a81e64..4508bbea5df1 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -468,6 +468,9 @@ struct spi_nor_fixups {
* SPI_NOR_OCTAL_READ: flash supports Octal Read.
* SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
* SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
+ * SPI_NOR_DTR_SWAB16: the byte order of 16-bit words is swapped when
+ * read or written in Octal DTR mode compared to STR
+ * mode.
*
* @fixup_flags: flags that indicate support that can be discovered via SFDP
* ideally, but can not be discovered for this particular flash
@@ -507,7 +510,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
- u8 no_sfdp_flags;
+ u16 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
#define SECT_4K BIT(1)
#define SECT_4K_PMC BIT(2)
@@ -516,6 +519,7 @@ struct flash_info {
#define SPI_NOR_OCTAL_READ BIT(5)
#define SPI_NOR_OCTAL_DTR_READ BIT(6)
#define SPI_NOR_OCTAL_DTR_PP BIT(7)
+#define SPI_NOR_DTR_SWAB16 BIT(8)
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)
--
2.25.1
next prev parent reply other threads:[~2022-03-11 8:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 8:01 [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 1/6] spi: " Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 2/6] mtd: spi-nor: core: " Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 3/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Tudor Ambarus
2022-03-11 8:01 ` Tudor Ambarus [this message]
2022-03-11 8:01 ` [PATCH v2 5/6] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Tudor Ambarus
2022-03-11 8:01 ` [PATCH v2 6/6] mtd: spi-nor: macronix: Add support for mx66lm1g45g Tudor Ambarus
2022-03-15 6:08 ` [PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode Vignesh Raghavendra
2022-03-15 6:58 ` Tudor.Ambarus
2022-03-16 7:08 ` Vignesh Raghavendra
2022-03-16 8:39 ` Michael Walle
2022-03-15 7:19 ` Michael Walle
2022-03-16 7:05 ` Vignesh Raghavendra
2022-03-16 7:57 ` Tudor.Ambarus
2022-03-16 13:55 ` David Laight
2022-03-17 9:40 ` Michael Walle
2022-03-17 10:14 ` David Laight
2022-03-17 10:23 ` Vignesh Raghavendra
2022-03-17 11:10 ` David Laight
2022-03-17 16:49 ` Vignesh Raghavendra
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