* [PATCH v6 1/6] RISC-V: Correctly print supported extensions
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-18 3:41 ` Joe Perches
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Tsukasa OI, Anup Patel, Heiko Stuebner, Atish Patra, Albert Ou,
Atish Patra, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
From: Tsukasa OI <research_trasio@irq.a4lg.com>
This commit replaces BITS_PER_LONG with number of alphabet letters.
Current ISA pretty-printing code expects extension 'a' (bit 0) through
'z' (bit 25). Although bit 26 and higher is not currently used (thus never
cause an issue in practice), it will be an annoying problem if we start to
use those in the future.
This commit disables printing high bits for now.
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..dd3d57eb4eea 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -13,6 +13,8 @@
#include <asm/smp.h>
#include <asm/switch_to.h>
+#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
+
unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
@@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void)
{
struct device_node *node;
const char *isa;
- char print_str[BITS_PER_LONG + 1];
+ char print_str[NUM_ALPHA_EXTS + 1];
size_t i, j, isa_len;
static unsigned long isa2hwcap[256] = {0};
@@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
}
memset(print_str, 0, sizeof(print_str));
- for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
if (riscv_isa[0] & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ISA extensions %s\n", print_str);
memset(print_str, 0, sizeof(print_str));
- for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
if (elf_hwcap & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ELF capabilities %s\n", print_str);
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 1/6] RISC-V: Correctly print supported extensions
2022-03-14 20:38 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Atish Patra
@ 2022-03-18 3:41 ` Joe Perches
0 siblings, 0 replies; 13+ messages in thread
From: Joe Perches @ 2022-03-18 3:41 UTC (permalink / raw)
To: Atish Patra, linux-kernel
Cc: Tsukasa OI, Anup Patel, Heiko Stuebner, Albert Ou, Atish Patra,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
On Mon, 2022-03-14 at 13:38 -0700, Atish Patra wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> This commit replaces BITS_PER_LONG with number of alphabet letters.
[]
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
[]
> @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
> }
>
> memset(print_str, 0, sizeof(print_str));
> - for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> if (riscv_isa[0] & BIT_MASK(i))
> print_str[j++] = (char)('a' + i);
probably better to add braces for the for loops too
> pr_info("riscv: ISA extensions %s\n", print_str);
>
> memset(print_str, 0, sizeof(print_str));
> - for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> if (elf_hwcap & BIT_MASK(i))
> print_str[j++] = (char)('a' + i);
> pr_info("riscv: ELF capabilities %s\n", print_str);
and here.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-03-14 20:38 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-15 3:08 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Tsukasa OI, Atish Patra, Heiko Stuebner, Albert Ou, Atish Patra,
Anup Patel, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Current hart ISA ("riscv,isa") parser don't correctly parse:
1. Multi-letter extensions
2. Version numbers
All ISA extensions ratified recently has multi-letter extensions
(except 'H'). The current "riscv,isa" parser that is easily confused
by multi-letter extensions and "p" in version numbers can be a huge
problem for adding new extensions through the device tree.
Leaving it would create incompatible hacks and would make "riscv,isa"
value unreliable.
This commit implements minimal parser for "riscv,isa" strings. With this,
we can safely ignore multi-letter extensions and version numbers.
[Improved commit text and fixed a bug around 's' in base extension]
Signed-off-by: Atish Patra <atishp@rivosinc.com>
[Fixed workaround for QEMU]
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------
1 file changed, 61 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index dd3d57eb4eea..72c5f6ef56b5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -7,6 +7,7 @@
*/
#include <linux/bitmap.h>
+#include <linux/ctype.h>
#include <linux/of.h>
#include <asm/processor.h>
#include <asm/hwcap.h>
@@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void)
struct device_node *node;
const char *isa;
char print_str[NUM_ALPHA_EXTS + 1];
- size_t i, j, isa_len;
+ int i, j;
static unsigned long isa2hwcap[256] = {0};
isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
@@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void)
continue;
}
- i = 0;
- isa_len = strlen(isa);
#if IS_ENABLED(CONFIG_32BIT)
if (!strncmp(isa, "rv32", 4))
- i += 4;
+ isa += 4;
#elif IS_ENABLED(CONFIG_64BIT)
if (!strncmp(isa, "rv64", 4))
- i += 4;
+ isa += 4;
#endif
- for (; i < isa_len; ++i) {
- this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
+ for (; *isa; ++isa) {
+ const char *ext = isa++;
+ const char *ext_end = isa;
+ bool ext_long = false, ext_err = false;
+
+ switch (*ext) {
+ case 's':
+ /**
+ * Workaround for invalid single-letter 's' & 'u'(QEMU).
+ * No need to set the bit in riscv_isa as 's' & 'u' are
+ * not valid ISA extensions. It works until multi-letter
+ * extension starting with "Su" appears.
+ */
+ if (ext[-1] != '_' && ext[1] == 'u') {
+ ++isa;
+ ext_err = true;
+ break;
+ }
+ fallthrough;
+ case 'x':
+ case 'z':
+ ext_long = true;
+ /* Multi-letter extension must be delimited */
+ for (; *isa && *isa != '_'; ++isa)
+ if (!islower(*isa) && !isdigit(*isa))
+ ext_err = true;
+ break;
+ default:
+ if (unlikely(!islower(*ext))) {
+ ext_err = true;
+ break;
+ }
+ /* Find next extension */
+ if (!isdigit(*isa))
+ break;
+ /* Skip the minor version */
+ while (isdigit(*++isa))
+ ;
+ if (*isa != 'p')
+ break;
+ if (!isdigit(*++isa)) {
+ --isa;
+ break;
+ }
+ /* Skip the major version */
+ while (isdigit(*++isa))
+ ;
+ break;
+ }
+ if (*isa != '_')
+ --isa;
/*
- * TODO: X, Y and Z extension parsing for Host ISA
- * bitmap will be added in-future.
+ * TODO: Full version-aware handling including
+ * multi-letter extensions will be added in-future.
*/
- if ('a' <= isa[i] && isa[i] < 'x')
- this_isa |= (1UL << (isa[i] - 'a'));
+ if (ext_err || ext_long)
+ continue;
+ this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
+ this_isa |= (1UL << (*ext - 'a'));
}
/*
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
@ 2022-03-15 3:08 ` Anup Patel
0 siblings, 0 replies; 13+ messages in thread
From: Anup Patel @ 2022-03-15 3:08 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel@vger.kernel.org List, Tsukasa OI, Heiko Stuebner,
Albert Ou, Atish Patra, Damien Le Moal, DTML, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
On Tue, Mar 15, 2022 at 2:09 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Current hart ISA ("riscv,isa") parser don't correctly parse:
>
> 1. Multi-letter extensions
> 2. Version numbers
>
> All ISA extensions ratified recently has multi-letter extensions
> (except 'H'). The current "riscv,isa" parser that is easily confused
> by multi-letter extensions and "p" in version numbers can be a huge
> problem for adding new extensions through the device tree.
>
> Leaving it would create incompatible hacks and would make "riscv,isa"
> value unreliable.
>
> This commit implements minimal parser for "riscv,isa" strings. With this,
> we can safely ignore multi-letter extensions and version numbers.
>
> [Improved commit text and fixed a bug around 's' in base extension]
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> [Fixed workaround for QEMU]
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
I think I have reviewed most of the patches in this series.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------
> 1 file changed, 61 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index dd3d57eb4eea..72c5f6ef56b5 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -7,6 +7,7 @@
> */
>
> #include <linux/bitmap.h>
> +#include <linux/ctype.h>
> #include <linux/of.h>
> #include <asm/processor.h>
> #include <asm/hwcap.h>
> @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void)
> struct device_node *node;
> const char *isa;
> char print_str[NUM_ALPHA_EXTS + 1];
> - size_t i, j, isa_len;
> + int i, j;
> static unsigned long isa2hwcap[256] = {0};
>
> isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
> @@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void)
> continue;
> }
>
> - i = 0;
> - isa_len = strlen(isa);
> #if IS_ENABLED(CONFIG_32BIT)
> if (!strncmp(isa, "rv32", 4))
> - i += 4;
> + isa += 4;
> #elif IS_ENABLED(CONFIG_64BIT)
> if (!strncmp(isa, "rv64", 4))
> - i += 4;
> + isa += 4;
> #endif
> - for (; i < isa_len; ++i) {
> - this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> + for (; *isa; ++isa) {
> + const char *ext = isa++;
> + const char *ext_end = isa;
> + bool ext_long = false, ext_err = false;
> +
> + switch (*ext) {
> + case 's':
> + /**
> + * Workaround for invalid single-letter 's' & 'u'(QEMU).
> + * No need to set the bit in riscv_isa as 's' & 'u' are
> + * not valid ISA extensions. It works until multi-letter
> + * extension starting with "Su" appears.
> + */
> + if (ext[-1] != '_' && ext[1] == 'u') {
> + ++isa;
> + ext_err = true;
> + break;
> + }
> + fallthrough;
> + case 'x':
> + case 'z':
> + ext_long = true;
> + /* Multi-letter extension must be delimited */
> + for (; *isa && *isa != '_'; ++isa)
> + if (!islower(*isa) && !isdigit(*isa))
> + ext_err = true;
> + break;
> + default:
> + if (unlikely(!islower(*ext))) {
> + ext_err = true;
> + break;
> + }
> + /* Find next extension */
> + if (!isdigit(*isa))
> + break;
> + /* Skip the minor version */
> + while (isdigit(*++isa))
> + ;
> + if (*isa != 'p')
> + break;
> + if (!isdigit(*++isa)) {
> + --isa;
> + break;
> + }
> + /* Skip the major version */
> + while (isdigit(*++isa))
> + ;
> + break;
> + }
> + if (*isa != '_')
> + --isa;
> /*
> - * TODO: X, Y and Z extension parsing for Host ISA
> - * bitmap will be added in-future.
> + * TODO: Full version-aware handling including
> + * multi-letter extensions will be added in-future.
> */
> - if ('a' <= isa[i] && isa[i] < 'x')
> - this_isa |= (1UL << (isa[i] - 'a'));
> + if (ext_err || ext_long)
> + continue;
> + this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
> + this_isa |= (1UL << (*ext - 'a'));
> }
>
> /*
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa"
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-03-14 20:38 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Tsukasa OI, Heiko Stuebner, Anup Patel, Atish Patra, Albert Ou,
Atish Patra, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Currently, there is no usage for version numbers in extensions as
any ratified non base ISA extension will always at v1.0.
Extract the extension names in place for future parsing.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
[Improved commit text and comments]
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 35 ++++++++++++++++++++++++++--------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 72c5f6ef56b5..b0df7eff47f7 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -124,8 +124,28 @@ void __init riscv_fill_hwcap(void)
ext_long = true;
/* Multi-letter extension must be delimited */
for (; *isa && *isa != '_'; ++isa)
- if (!islower(*isa) && !isdigit(*isa))
+ if (unlikely(!islower(*isa)
+ && !isdigit(*isa)))
ext_err = true;
+ /* Parse backwards */
+ ext_end = isa;
+ if (unlikely(ext_err))
+ break;
+ if (!isdigit(ext_end[-1]))
+ break;
+ /* Skip the minor version */
+ while (isdigit(*--ext_end))
+ ;
+ if (ext_end[0] != 'p'
+ || !isdigit(ext_end[-1])) {
+ /* Advance it to offset the pre-decrement */
+ ++ext_end;
+ break;
+ }
+ /* Skip the major version */
+ while (isdigit(*--ext_end))
+ ;
+ ++ext_end;
break;
default:
if (unlikely(!islower(*ext))) {
@@ -151,14 +171,13 @@ void __init riscv_fill_hwcap(void)
}
if (*isa != '_')
--isa;
- /*
- * TODO: Full version-aware handling including
- * multi-letter extensions will be added in-future.
- */
- if (ext_err || ext_long)
+
+ if (unlikely(ext_err))
continue;
- this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
- this_isa |= (1UL << (*ext - 'a'));
+ if (!ext_long) {
+ this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
+ this_isa |= (1UL << (*ext - 'a'));
+ }
}
/*
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
` (2 preceding siblings ...)
2022-03-14 20:38 ` [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Heiko Stuebner, Albert Ou, Atish Patra, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
Multi-letter extensions can be probed using exising
riscv_isa_extension_available API now. It doesn't support versioning
right now as there is no use case for it.
Individual extension specific implementation will be added during
each extension support.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++
arch/riscv/kernel/cpufeature.c | 22 ++++++++++++++++------
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5ce50468aff1..170bd80da520 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -34,7 +34,25 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
+/*
+ * Increse this to higher value as kernel support more ISA extensions.
+ */
#define RISCV_ISA_EXT_MAX 64
+#define RISCV_ISA_EXT_NAME_LEN_MAX 32
+
+/* The base ID for multi-letter ISA extensions */
+#define RISCV_ISA_EXT_BASE 26
+
+/*
+ * This enum represent the logical ID for each multi-letter RISC-V ISA extension.
+ * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
+ * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
+ * extensions while all the multi-letter extensions should define the next
+ * available logical extension id.
+ */
+enum riscv_isa_ext_id {
+ RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
+};
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b0df7eff47f7..3455fdfd680e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void)
for_each_of_cpu_node(node) {
unsigned long this_hwcap = 0;
- unsigned long this_isa = 0;
+ DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
if (riscv_of_processor_hartid(node) < 0)
continue;
@@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void)
if (!strncmp(isa, "rv64", 4))
isa += 4;
#endif
+ bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
const char *ext_end = isa;
@@ -172,12 +173,20 @@ void __init riscv_fill_hwcap(void)
if (*isa != '_')
--isa;
+#define SET_ISA_EXT_MAP(name, bit) \
+ do { \
+ if ((ext_end - ext == sizeof(name) - 1) && \
+ !memcmp(ext, name, sizeof(name) - 1)) \
+ set_bit(bit, this_isa); \
+ } while (false) \
+
if (unlikely(ext_err))
continue;
if (!ext_long) {
this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
- this_isa |= (1UL << (*ext - 'a'));
+ set_bit(*ext - 'a', this_isa);
}
+#undef SET_ISA_EXT_MAP
}
/*
@@ -190,10 +199,11 @@ void __init riscv_fill_hwcap(void)
else
elf_hwcap = this_hwcap;
- if (riscv_isa[0])
- riscv_isa[0] &= this_isa;
+ if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX))
+ bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
else
- riscv_isa[0] = this_isa;
+ bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+
}
/* We don't support systems with F but without D, so mask those out
@@ -207,7 +217,7 @@ void __init riscv_fill_hwcap(void)
for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
if (riscv_isa[0] & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
- pr_info("riscv: ISA extensions %s\n", print_str);
+ pr_info("riscv: base ISA extensions %s\n", print_str);
memset(print_str, 0, sizeof(print_str));
for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
@ 2022-03-15 3:09 ` Anup Patel
0 siblings, 0 replies; 13+ messages in thread
From: Anup Patel @ 2022-03-15 3:09 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel@vger.kernel.org List, Heiko Stuebner, Albert Ou,
Atish Patra, Damien Le Moal, DTML, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
On Tue, Mar 15, 2022 at 2:09 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Multi-letter extensions can be probed using exising
> riscv_isa_extension_available API now. It doesn't support versioning
> right now as there is no use case for it.
> Individual extension specific implementation will be added during
> each extension support.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++
> arch/riscv/kernel/cpufeature.c | 22 ++++++++++++++++------
> 2 files changed, 34 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5ce50468aff1..170bd80da520 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap;
> #define RISCV_ISA_EXT_s ('s' - 'a')
> #define RISCV_ISA_EXT_u ('u' - 'a')
>
> +/*
> + * Increse this to higher value as kernel support more ISA extensions.
> + */
> #define RISCV_ISA_EXT_MAX 64
> +#define RISCV_ISA_EXT_NAME_LEN_MAX 32
> +
> +/* The base ID for multi-letter ISA extensions */
> +#define RISCV_ISA_EXT_BASE 26
> +
> +/*
> + * This enum represent the logical ID for each multi-letter RISC-V ISA extension.
> + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
> + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
> + * extensions while all the multi-letter extensions should define the next
> + * available logical extension id.
> + */
> +enum riscv_isa_ext_id {
> + RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> +};
>
> unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b0df7eff47f7..3455fdfd680e 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void)
>
> for_each_of_cpu_node(node) {
> unsigned long this_hwcap = 0;
> - unsigned long this_isa = 0;
> + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>
> if (riscv_of_processor_hartid(node) < 0)
> continue;
> @@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void)
> if (!strncmp(isa, "rv64", 4))
> isa += 4;
> #endif
> + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
> for (; *isa; ++isa) {
> const char *ext = isa++;
> const char *ext_end = isa;
> @@ -172,12 +173,20 @@ void __init riscv_fill_hwcap(void)
> if (*isa != '_')
> --isa;
>
> +#define SET_ISA_EXT_MAP(name, bit) \
> + do { \
> + if ((ext_end - ext == sizeof(name) - 1) && \
> + !memcmp(ext, name, sizeof(name) - 1)) \
> + set_bit(bit, this_isa); \
> + } while (false) \
> +
> if (unlikely(ext_err))
> continue;
> if (!ext_long) {
> this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
> - this_isa |= (1UL << (*ext - 'a'));
> + set_bit(*ext - 'a', this_isa);
> }
> +#undef SET_ISA_EXT_MAP
> }
>
> /*
> @@ -190,10 +199,11 @@ void __init riscv_fill_hwcap(void)
> else
> elf_hwcap = this_hwcap;
>
> - if (riscv_isa[0])
> - riscv_isa[0] &= this_isa;
> + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX))
> + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> else
> - riscv_isa[0] = this_isa;
> + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> +
> }
>
> /* We don't support systems with F but without D, so mask those out
> @@ -207,7 +217,7 @@ void __init riscv_fill_hwcap(void)
> for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> if (riscv_isa[0] & BIT_MASK(i))
> print_str[j++] = (char)('a' + i);
> - pr_info("riscv: ISA extensions %s\n", print_str);
> + pr_info("riscv: base ISA extensions %s\n", print_str);
>
> memset(print_str, 0, sizeof(print_str));
> for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
` (3 preceding siblings ...)
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-03-18 3:10 ` [PATCH v6 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
6 siblings, 1 reply; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Heiko Stuebner, Albert Ou, Atish Patra, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
The isa string should begin with either rv64 or rv32. Otherwise, it is
an incorrect isa string. Currently, the string parsing continues even if
it doesnot begin with current XLEN.
Fix this by checking if it found "rv64" or "rv32" in the beginning.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3455fdfd680e..a43c08af5f4b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
for_each_of_cpu_node(node) {
unsigned long this_hwcap = 0;
DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+ const char *temp;
if (riscv_of_processor_hartid(node) < 0)
continue;
@@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
continue;
}
+ temp = isa;
#if IS_ENABLED(CONFIG_32BIT)
if (!strncmp(isa, "rv32", 4))
isa += 4;
@@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void)
if (!strncmp(isa, "rv64", 4))
isa += 4;
#endif
+ /* The riscv,isa DT property must start with rv64 or rv32 */
+ if (temp == isa)
+ continue;
bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
2022-03-14 20:38 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
@ 2022-03-15 3:09 ` Anup Patel
0 siblings, 0 replies; 13+ messages in thread
From: Anup Patel @ 2022-03-15 3:09 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel@vger.kernel.org List, Heiko Stuebner, Albert Ou,
Atish Patra, Damien Le Moal, DTML, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
On Tue, Mar 15, 2022 at 2:09 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The isa string should begin with either rv64 or rv32. Otherwise, it is
> an incorrect isa string. Currently, the string parsing continues even if
> it doesnot begin with current XLEN.
>
> Fix this by checking if it found "rv64" or "rv32" in the beginning.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> arch/riscv/kernel/cpufeature.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3455fdfd680e..a43c08af5f4b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> for_each_of_cpu_node(node) {
> unsigned long this_hwcap = 0;
> DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
> + const char *temp;
>
> if (riscv_of_processor_hartid(node) < 0)
> continue;
> @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> continue;
> }
>
> + temp = isa;
> #if IS_ENABLED(CONFIG_32BIT)
> if (!strncmp(isa, "rv32", 4))
> isa += 4;
> @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void)
> if (!strncmp(isa, "rv64", 4))
> isa += 4;
> #endif
> + /* The riscv,isa DT property must start with rv64 or rv32 */
> + if (temp == isa)
> + continue;
> bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
> for (; *isa; ++isa) {
> const char *ext = isa++;
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
` (4 preceding siblings ...)
2022-03-14 20:38 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
@ 2022-03-14 20:38 ` Atish Patra
2022-03-15 3:11 ` Anup Patel
2022-03-18 3:10 ` [PATCH v6 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
6 siblings, 1 reply; 13+ messages in thread
From: Atish Patra @ 2022-03-14 20:38 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Heiko Stuebner, Albert Ou, Atish Patra, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
Currently, the /proc/cpuinfo outputs the entire riscv,isa string which
is not ideal when we have multiple ISA extensions present in the ISA
string. Some of them may not be enabled in kernel as well.
Same goes for the single letter extensions as well which prints the
entire ISA string. Some of they may not be valid ISA extensions as
well (e.g 'su')
Parse only the valid & enabled ISA extension and print them.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/hwcap.h | 7 ++++
arch/riscv/kernel/cpu.c | 65 ++++++++++++++++++++++++++++++++--
2 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 170bd80da520..691fc9c8099b 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -54,6 +54,13 @@ enum riscv_isa_ext_id {
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
+struct riscv_isa_ext_data {
+ /* Name of the extension displayed to userspace via /proc/cpuinfo */
+ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
+ /* The logical ISA extension ID */
+ unsigned int isa_ext_id;
+};
+
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index ad0a7e9f828b..fc115e307ef5 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -6,6 +6,7 @@
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/of.h>
+#include <asm/hwcap.h>
#include <asm/smp.h>
#include <asm/pgtable.h>
@@ -63,12 +64,72 @@ int riscv_of_parent_hartid(struct device_node *node)
}
#ifdef CONFIG_PROC_FS
+#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
+ { \
+ .uprop = #UPROP, \
+ .isa_ext_id = EXTID, \
+ }
+/**
+ * Here are the ordering rules of extension naming defined by RISC-V
+ * specification :
+ * 1. All extensions should be separated from other multi-letter extensions
+ * from other multi-letter extensions by an underscore.
+ * 2. The first letter following the 'Z' conventionally indicates the most
+ * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ * If multiple 'Z' extensions are named, they should be ordered first
+ * by category, then alphabetically within a category.
+ * 3. Standard supervisor-level extensions (starts with 'S') should be
+ * listed after standard unprivileged extensions. If multiple
+ * supervisor-level extensions are listed, they should be ordered
+ * alphabetically.
+ * 4. Non-standard extensions (starts with 'X') must be listed after all
+ * standard extensions. They must be separated from other multi-letter
+ * extensions by an underscore.
+ */
+static struct riscv_isa_ext_data isa_ext_arr[] = {
+ __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
+};
+
+static void print_isa_ext(struct seq_file *f)
+{
+ struct riscv_isa_ext_data *edata;
+ int i = 0, arr_sz;
+
+ arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
+
+ /* No extension support available */
+ if (arr_sz <= 0)
+ return;
+
+ for (i = 0; i <= arr_sz; i++) {
+ edata = &isa_ext_arr[i];
+ if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+ continue;
+ seq_printf(f, "_%s", edata->uprop);
+ }
+}
+
+/**
+ * These are the only valid base (single letter) ISA extensions as per the spec.
+ * It also specifies the canonical order in which it appears in the spec.
+ * Some of the extension may just be a place holder for now (B, K, P, J).
+ * This should be updated once corresponding extensions are ratified.
+ */
+static const char base_riscv_exts[13] = "imafdqcbkjpvh";
static void print_isa(struct seq_file *f, const char *isa)
{
- /* Print the entire ISA as it is */
+ int i;
+
seq_puts(f, "isa\t\t: ");
- seq_write(f, isa, strlen(isa));
+ /* Print the rv[64/32] part */
+ seq_write(f, isa, 4);
+ for (i = 0; i < sizeof(base_riscv_exts); i++) {
+ if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
+ /* Print only enabled the base ISA extensions */
+ seq_write(f, &base_riscv_exts[i], 1);
+ }
+ print_isa_ext(f);
seq_puts(f, "\n");
}
--
2.30.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
@ 2022-03-15 3:11 ` Anup Patel
0 siblings, 0 replies; 13+ messages in thread
From: Anup Patel @ 2022-03-15 3:11 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel@vger.kernel.org List, Heiko Stuebner, Albert Ou,
Atish Patra, Damien Le Moal, DTML, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
On Tue, Mar 15, 2022 at 2:09 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Currently, the /proc/cpuinfo outputs the entire riscv,isa string which
> is not ideal when we have multiple ISA extensions present in the ISA
> string. Some of them may not be enabled in kernel as well.
> Same goes for the single letter extensions as well which prints the
> entire ISA string. Some of they may not be valid ISA extensions as
> well (e.g 'su')
>
> Parse only the valid & enabled ISA extension and print them.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> arch/riscv/include/asm/hwcap.h | 7 ++++
> arch/riscv/kernel/cpu.c | 65 ++++++++++++++++++++++++++++++++--
> 2 files changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 170bd80da520..691fc9c8099b 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -54,6 +54,13 @@ enum riscv_isa_ext_id {
> RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> };
>
> +struct riscv_isa_ext_data {
> + /* Name of the extension displayed to userspace via /proc/cpuinfo */
> + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
> + /* The logical ISA extension ID */
> + unsigned int isa_ext_id;
> +};
> +
> unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
>
> #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ad0a7e9f828b..fc115e307ef5 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -6,6 +6,7 @@
> #include <linux/init.h>
> #include <linux/seq_file.h>
> #include <linux/of.h>
> +#include <asm/hwcap.h>
> #include <asm/smp.h>
> #include <asm/pgtable.h>
>
> @@ -63,12 +64,72 @@ int riscv_of_parent_hartid(struct device_node *node)
> }
>
> #ifdef CONFIG_PROC_FS
> +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
> + { \
> + .uprop = #UPROP, \
> + .isa_ext_id = EXTID, \
> + }
> +/**
> + * Here are the ordering rules of extension naming defined by RISC-V
> + * specification :
> + * 1. All extensions should be separated from other multi-letter extensions
> + * from other multi-letter extensions by an underscore.
> + * 2. The first letter following the 'Z' conventionally indicates the most
> + * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
> + * If multiple 'Z' extensions are named, they should be ordered first
> + * by category, then alphabetically within a category.
> + * 3. Standard supervisor-level extensions (starts with 'S') should be
> + * listed after standard unprivileged extensions. If multiple
> + * supervisor-level extensions are listed, they should be ordered
> + * alphabetically.
> + * 4. Non-standard extensions (starts with 'X') must be listed after all
> + * standard extensions. They must be separated from other multi-letter
> + * extensions by an underscore.
> + */
> +static struct riscv_isa_ext_data isa_ext_arr[] = {
> + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> +};
> +
> +static void print_isa_ext(struct seq_file *f)
> +{
> + struct riscv_isa_ext_data *edata;
> + int i = 0, arr_sz;
> +
> + arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
> +
> + /* No extension support available */
> + if (arr_sz <= 0)
> + return;
> +
> + for (i = 0; i <= arr_sz; i++) {
> + edata = &isa_ext_arr[i];
> + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
> + continue;
> + seq_printf(f, "_%s", edata->uprop);
> + }
> +}
> +
> +/**
> + * These are the only valid base (single letter) ISA extensions as per the spec.
> + * It also specifies the canonical order in which it appears in the spec.
> + * Some of the extension may just be a place holder for now (B, K, P, J).
> + * This should be updated once corresponding extensions are ratified.
> + */
> +static const char base_riscv_exts[13] = "imafdqcbkjpvh";
>
> static void print_isa(struct seq_file *f, const char *isa)
> {
> - /* Print the entire ISA as it is */
> + int i;
> +
> seq_puts(f, "isa\t\t: ");
> - seq_write(f, isa, strlen(isa));
> + /* Print the rv[64/32] part */
> + seq_write(f, isa, 4);
> + for (i = 0; i < sizeof(base_riscv_exts); i++) {
> + if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
> + /* Print only enabled the base ISA extensions */
> + seq_write(f, &base_riscv_exts[i], 1);
> + }
> + print_isa_ext(f);
> seq_puts(f, "\n");
> }
>
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
` (5 preceding siblings ...)
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
@ 2022-03-18 3:10 ` Palmer Dabbelt
6 siblings, 0 replies; 13+ messages in thread
From: Palmer Dabbelt @ 2022-03-18 3:10 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel, Atish Patra, aou, atishp, anup, damien.lemoal,
devicetree, jszhang, krzysztof.kozlowski, linux-riscv,
Paul Walmsley, robh+dt
On Mon, 14 Mar 2022 13:38:39 PDT (-0700), Atish Patra wrote:
> This series implements a generic framework to parse multi-letter ISA
> extensions. This series is based on Tsukasa's v3 isa extension improvement
> series[1]. I have fixed few bugs and improved comments from that series
> (PATCH1-3). I have not used PATCH 4 from that series as we are not using
> ISA extension versioning as of now. We can add that later if required.
>
> PATCH 4 allows the probing of multi-letter extensions via a macro.
> It continues to use the common isa extensions between all the harts.
> Thus hetergenous hart systems will only see the common ISA extensions.
>
> PATCH 6 improves the /proc/cpuinfo interface for the available ISA extensions
> via /proc/cpuinfo.
>
> Here is the example output of /proc/cpuinfo:
> (with debug patches in Qemu and Linux kernel)
>
> / # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdch_svpbmt_svnapot_svinval
> mmu : sv48
>
> processor : 1
> hart : 1
> isa : rv64imafdch_svpbmt_svnapot_svinval
> mmu : sv48
>
> processor : 2
> hart : 2
> isa : rv64imafdch_svpbmt_svnapot_svinval
> mmu : sv48
>
> processor : 3
> hart : 3
> isa : rv64imafdch_svpbmt_svnapot_svinval
> mmu : sv48
>
> Anybody adding support for any new multi-letter extensions should add an
> entry to the riscv_isa_ext_id and the isa extension array.
> E.g. The patch[2] adds the support for various ISA extensions.
>
> [1] https://lore.kernel.org/all/0f568515-a05e-8204-aae3-035975af3ee8@irq.a4lg.com/T/
> [2] https://github.com/atishp04/linux/commit/e9e240c9a854dceb434ceb53bdbe82a657bee5f2
>
> Changes from v5->v6:
> 1. Changed the isa extension format from separate row to single row that follows
> RISC-V spec naming standards.
>
> 2. Removed the redundant extension detection log.
>
> Changes from v4->v5:
> 1. Improved the /proc/cpuinfo to include only valid & enabled extensions
> 2. Improved the multi-letter parsing by skipping the 'su' modes generated in
> Qemu as suggested by Tsukasa.
>
> Changes from v3->v4:
> 1. Changed temporary variable for current hart isa to a bitmap
> 2. Added reviewed-by tags.
> 3. Improved comments
>
> Changes from v2->v3:
> 1. Updated comments to mark clearly a fix required for Qemu only.
> 2. Fixed a bug where the 1st multi-letter extension can be present without _
> 3. Added Tested by tags.
>
> Changes from v1->v2:
> 1. Instead of adding a separate DT property use the riscv,isa property.
> 2. Based on Tsukasa's v3 isa extension improvement series.
>
> Atish Patra (3):
> RISC-V: Implement multi-letter ISA extension probing framework
> RISC-V: Do no continue isa string parsing without correct XLEN
> RISC-V: Improve /proc/cpuinfo output for ISA extensions
>
> Tsukasa OI (3):
> RISC-V: Correctly print supported extensions
> RISC-V: Minimal parser for "riscv, isa" strings
> RISC-V: Extract multi-letter extension names from "riscv, isa"
>
> arch/riscv/include/asm/hwcap.h | 25 +++++++
> arch/riscv/kernel/cpu.c | 65 ++++++++++++++++-
> arch/riscv/kernel/cpufeature.c | 128 +++++++++++++++++++++++++++------
> 3 files changed, 195 insertions(+), 23 deletions(-)
Thanks, this is on for-next.
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