* [PATCH v5 1/7] ethtool: Add 10base-T1L link mode entry
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 2/7] net: phy: Add 10-BaseT1L registers alexandru.tachici
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
Add entry for the 10base-T1L full duplex mode.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
drivers/net/phy/phy-core.c | 3 ++-
include/uapi/linux/ethtool.h | 1 +
net/ethtool/common.c | 3 +++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 2001f3329133..1f2531a1a876 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@@ -176,6 +176,7 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 7bc4b8def12c..e0f0ee9bc89e 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1691,6 +1691,7 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 0c5210015911..566adf85e658 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -201,6 +201,7 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(400000, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -236,6 +237,7 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
#define __LINK_MODE_LANES_T1 1
#define __LINK_MODE_LANES_X 1
#define __LINK_MODE_LANES_FX 1
+#define __LINK_MODE_LANES_T1L 1
#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
@@ -349,6 +351,7 @@ const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 2/7] net: phy: Add 10-BaseT1L registers
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 1/7] ethtool: Add 10base-T1L link mode entry alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 3/7] net: phy: Add BaseT1 auto-negotiation registers alexandru.tachici
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
The 802.3gc specification defines the 10-BaseT1L link
mode for ethernet trafic on twisted wire pair.
PMA status register can be used to detect if the phy supports
2.4 V TX level and PCS control register can be used to
enable/disable PCS level loopback.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
include/uapi/linux/mdio.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index c54e6eae5366..0b2eba36dd7c 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -67,6 +67,9 @@
#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
+#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
+#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
+#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -268,6 +271,28 @@
#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
+/* 10BASE-T1L PMA control */
+#define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001 /* Enable loopback mode */
+#define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400 /* Enable EEE mode */
+#define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 /* Low-power mode */
+#define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000 /* Enable 2.4 Vpp operating mode */
+#define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000 /* Transmit disable */
+#define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000 /* MA reset */
+
+/* 10BASE-T1L PMA status register. */
+#define MDIO_PMA_10T1L_STAT_LINK 0x0001 /* PMA receive link up */
+#define MDIO_PMA_10T1L_STAT_FAULT 0x0002 /* Fault condition detected */
+#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 /* Receive polarity is reversed */
+#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 /* Able to detect fault on receive path */
+#define MDIO_PMA_10T1L_STAT_EEE 0x0400 /* PHY has EEE ability */
+#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */
+#define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 /* PHY has 2.4 Vpp operating mode ability */
+#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */
+
+/* 10BASE-T1L PCS control register. */
+#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
+#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
+
/* EEE Supported/Advertisement/LP Advertisement registers.
*
* EEE capability Register (3.20), Advertisement (7.60) and
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 3/7] net: phy: Add BaseT1 auto-negotiation registers
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 1/7] ethtool: Add 10base-T1L link mode entry alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 2/7] net: phy: Add 10-BaseT1L registers alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 4/7] net: phy: Add 10BASE-T1L support in phy-c45 alexandru.tachici
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
Added BASE-T1 AN advertisement register (Registers 7.514, 7.515, and
7.516) and BASE-T1 AN LP Base Page ability register (Registers 7.517,
7.518, and 7.519).
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
include/uapi/linux/mdio.h | 40 +++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 0b2eba36dd7c..fa3515257f54 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -70,6 +70,14 @@
#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
+#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
+#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
+#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
+#define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */
+#define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */
+#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
+#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
+#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -293,6 +301,38 @@
#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
+/* BASE-T1 auto-negotiation advertisement register [15:0] */
+#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
+#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
+#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 /* Force Master/slave Configuration */
+#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
+#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
+#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
+
+/* BASE-T1 auto-negotiation advertisement register [31:16] */
+#define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
+#define MDIO_AN_T1_ADV_M_MST 0x0010 /* advertise master preference */
+
+/* BASE-T1 auto-negotiation advertisement register [47:32] */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
+
+/* BASE-T1 AN LP Base Page ability register [15:0] */
+#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
+#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
+#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 /* LP Force Master/slave Configuration */
+#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
+#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
+#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
+
+/* BASE-T1 AN LP Base Page ability register [31:16] */
+#define MDIO_AN_T1_LP_M_MST 0x0010 /* LP master preference */
+#define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
+
+/* BASE-T1 AN LP Base Page ability register [47:32] */
+#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
+#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
+
/* EEE Supported/Advertisement/LP Advertisement registers.
*
* EEE capability Register (3.20), Advertisement (7.60) and
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 4/7] net: phy: Add 10BASE-T1L support in phy-c45
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (2 preceding siblings ...)
2022-03-24 11:26 ` [PATCH v5 3/7] net: phy: Add BaseT1 auto-negotiation registers alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
This patch is needed because the BASE-T1 uses different registers
for status, control and advertisement to those already
employed in the existing phy-c45 functions.
Where required, genphy_c45 functions will now check whether
the device supports BASE-T1 and use the specific registers
instead: 45.2.7.19 BASE-T1 AN control register,
45.2.7.20 BASE-T1 AN status, 45.2.7.21 BASE-T1 AN
advertisement register, 45.2.7.22 BASE-T1 AN LP Base
Page ability register, 45.2.1.185 BASE-T1 PMA/PMD control
register.
Tested-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
drivers/net/phy/phy-c45.c | 258 ++++++++++++++++++++++++++++++++++-
drivers/net/phy/phy_device.c | 1 +
include/linux/mdio.h | 70 ++++++++++
include/linux/phy.h | 2 +
include/uapi/linux/mdio.h | 10 ++
5 files changed, 336 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
index db709d30bf84..43d47954ba9c 100644
--- a/drivers/net/phy/phy-c45.c
+++ b/drivers/net/phy/phy-c45.c
@@ -8,6 +8,25 @@
#include <linux/mii.h>
#include <linux/phy.h>
+/**
+ * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
+ * @phydev: target phy_device struct
+ */
+static bool genphy_c45_baset1_able(struct phy_device *phydev)
+{
+ int val;
+
+ if (phydev->pma_extable == -ENODATA) {
+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
+ if (val < 0)
+ return false;
+
+ phydev->pma_extable = val;
+ }
+
+ return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
+}
+
/**
* genphy_c45_pma_can_sleep - checks if the PMA have sleep support
* @phydev: target phy_device struct
@@ -80,7 +99,10 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev)
switch (phydev->speed) {
case SPEED_10:
- ctrl2 |= MDIO_PMA_CTRL2_10BT;
+ if (genphy_c45_baset1_able(phydev))
+ ctrl2 |= MDIO_PMA_CTRL2_BASET1;
+ else
+ ctrl2 |= MDIO_PMA_CTRL2_10BT;
break;
case SPEED_100:
ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
@@ -118,10 +140,95 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev)
if (ret < 0)
return ret;
+ if (genphy_c45_baset1_able(phydev)) {
+ int ctl = 0;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ case MASTER_SLAVE_CFG_UNKNOWN:
+ case MASTER_SLAVE_CFG_UNSUPPORTED:
+ break;
+ default:
+ phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
+ MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
+ if (ret < 0)
+ return ret;
+ }
+
return genphy_c45_an_disable_aneg(phydev);
}
EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
+/* Sets master/slave preference and supported technologies.
+ * The preference is set in the BIT(4) of BASE-T1 AN
+ * advertisement register 7.515 and whether the status
+ * is forced or not, it is set in the BIT(12) of BASE-T1
+ * AN advertisement register 7.514.
+ * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
+ * advertisement register [31:16] if supported.
+ */
+static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
+{
+ int changed = 0;
+ u16 adv_l = 0;
+ u16 adv_m = 0;
+ int ret;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
+ break;
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ default:
+ break;
+ }
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ adv_m |= MDIO_AN_T1_ADV_M_MST;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ default:
+ break;
+ }
+
+ adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
+
+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
+ (MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP
+ | MDIO_AN_T1_ADV_L_PAUSE_ASYM), adv_l);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ changed = 1;
+
+ adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
+
+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
+ MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L, adv_m);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ changed = 1;
+
+ return changed;
+}
+
/**
* genphy_c45_an_config_aneg - configure advertisement registers
* @phydev: target phy_device struct
@@ -141,6 +248,9 @@ int genphy_c45_an_config_aneg(struct phy_device *phydev)
changed = genphy_config_eee_advert(phydev);
+ if (genphy_c45_baset1_able(phydev))
+ return genphy_c45_baset1_an_config_aneg(phydev);
+
adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
@@ -178,8 +288,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
*/
int genphy_c45_an_disable_aneg(struct phy_device *phydev)
{
+ u16 reg = MDIO_CTRL1;
- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
+ if (genphy_c45_baset1_able(phydev))
+ reg = MDIO_AN_T1_CTRL;
+
+ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
}
EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
@@ -194,7 +308,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
*/
int genphy_c45_restart_aneg(struct phy_device *phydev)
{
- return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
+ u16 reg = MDIO_CTRL1;
+
+ if (genphy_c45_baset1_able(phydev))
+ reg = MDIO_AN_T1_CTRL;
+
+ return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
}
EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
@@ -210,11 +329,15 @@ EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
*/
int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
{
+ u16 reg = MDIO_CTRL1;
int ret;
+ if (genphy_c45_baset1_able(phydev))
+ reg = MDIO_AN_T1_CTRL;
+
if (!restart) {
/* Configure and restart aneg if it wasn't set before */
- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
if (ret < 0)
return ret;
@@ -242,7 +365,13 @@ EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
*/
int genphy_c45_aneg_done(struct phy_device *phydev)
{
- int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ int reg = MDIO_STAT1;
+ int val;
+
+ if (genphy_c45_baset1_able(phydev))
+ reg = MDIO_AN_T1_STAT;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
}
@@ -307,6 +436,49 @@ int genphy_c45_read_link(struct phy_device *phydev)
}
EXPORT_SYMBOL_GPL(genphy_c45_read_link);
+/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
+ * if autoneg is complete. If so read the BASE-T1 Autonegotiation
+ * Advertisement registers filling in the link partner advertisement,
+ * pause and asym_pause members in phydev.
+ */
+static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
+{
+ int val;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
+ if (val < 0)
+ return val;
+
+ if (!(val & MDIO_AN_STAT1_COMPLETE)) {
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
+ mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
+ mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
+
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ return 0;
+ }
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
+ if (val < 0)
+ return val;
+
+ mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
+ phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
+ phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
+ if (val < 0)
+ return val;
+
+ mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
+
+ return 0;
+}
+
/**
* genphy_c45_read_lpa - read the link partner advertisement and pause
* @phydev: target phy_device struct
@@ -321,6 +493,9 @@ int genphy_c45_read_lpa(struct phy_device *phydev)
{
int val;
+ if (genphy_c45_baset1_able(phydev))
+ return genphy_c45_baset1_read_lpa(phydev);
+
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
if (val < 0)
return val;
@@ -399,6 +574,17 @@ int genphy_c45_read_pma(struct phy_device *phydev)
phydev->duplex = DUPLEX_FULL;
+ if (genphy_c45_baset1_able(phydev)) {
+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
+ if (val < 0)
+ return val;
+
+ if (MDIO_PMA_PMD_BT1_CTRL_CFG_MST)
+ phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
+ else
+ phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
@@ -530,12 +716,67 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev)
phydev->supported,
val & MDIO_PMA_NG_EXTABLE_5GBT);
}
+
+ if (val & MDIO_PMA_EXTABLE_BT1) {
+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ phydev->supported,
+ val & MDIO_PMA_PMD_BT1_B10L_ABLE);
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported,
+ val & MDIO_AN_STAT1_ABLE);
+ }
}
return 0;
}
EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
+/* Read master/slave preference from registers.
+ * The preference is read from the BIT(4) of BASE-T1 AN
+ * advertisement register 7.515 and whether the preference
+ * is forced or not, it is read from BASE-T1 AN advertisement
+ * register 7.514.
+ */
+static int genphy_c45_baset1_read_status(struct phy_device *phydev)
+{
+ int ret;
+ int cfg;
+
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
+ if (ret < 0)
+ return ret;
+
+ cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
+ if (cfg < 0)
+ return cfg;
+
+ if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
+ if (cfg & MDIO_AN_T1_ADV_M_MST)
+ phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
+ else
+ phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
+ } else {
+ if (cfg & MDIO_AN_T1_ADV_M_MST)
+ phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
+ else
+ phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
+ }
+
+ return 0;
+}
+
/**
* genphy_c45_read_status - read PHY status
* @phydev: target phy_device struct
@@ -545,6 +786,7 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
int genphy_c45_read_status(struct phy_device *phydev)
{
int ret;
+ int val;
ret = genphy_c45_read_link(phydev);
if (ret)
@@ -560,6 +802,12 @@ int genphy_c45_read_status(struct phy_device *phydev)
if (ret)
return ret;
+ if (genphy_c45_baset1_able(phydev)) {
+ ret = genphy_c45_baset1_read_status(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
phy_resolve_aneg_linkmode(phydev);
} else {
ret = genphy_c45_read_pma(phydev);
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 8406ac739def..5edf44f6f276 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -599,6 +599,7 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
dev->autoneg = AUTONEG_ENABLE;
+ dev->pma_extable = -ENODATA;
dev->is_c45 = is_c45;
dev->phy_id = phy_id;
if (c45_ids)
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index ecac96d52e01..00177567cfef 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -340,6 +340,76 @@ static inline void mii_10gbt_stat_mod_linkmode_lpa_t(unsigned long *advertising,
advertising, lpa & MDIO_AN_10GBT_STAT_LP10G);
}
+/**
+ * mii_t1_adv_l_mod_linkmode_t
+ * @advertising: target the linkmode advertisement settings
+ * @lpa: value of the BASE-T1 Autonegotiation Advertisement [15:0] Register
+ *
+ * A small helper function that translates BASE-T1 Autonegotiation
+ * Advertisement [15:0] Register bits to linkmode advertisement settings.
+ * Other bits in advertising aren't changed.
+ */
+static inline void mii_t1_adv_l_mod_linkmode_t(unsigned long *advertising, u32 lpa)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising,
+ lpa & MDIO_AN_T1_ADV_L_PAUSE_CAP);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising,
+ lpa & MDIO_AN_T1_ADV_L_PAUSE_ASYM);
+}
+
+/**
+ * mii_t1_adv_m_mod_linkmode_t
+ * @advertising: target the linkmode advertisement settings
+ * @lpa: value of the BASE-T1 Autonegotiation Advertisement [31:16] Register
+ *
+ * A small helper function that translates BASE-T1 Autonegotiation
+ * Advertisement [31:16] Register bits to linkmode advertisement settings.
+ * Other bits in advertising aren't changed.
+ */
+static inline void mii_t1_adv_m_mod_linkmode_t(unsigned long *advertising, u32 lpa)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ advertising, lpa & MDIO_AN_T1_ADV_M_B10L);
+}
+
+/**
+ * linkmode_adv_to_mii_t1_adv_l_t
+ * @advertising: the linkmode advertisement settings
+ *
+ * A small helper function that translates linkmode advertisement
+ * settings to phy autonegotiation advertisements for the
+ * BASE-T1 Autonegotiation Advertisement [15:0] Register.
+ */
+static inline u32 linkmode_adv_to_mii_t1_adv_l_t(unsigned long *advertising)
+{
+ u32 result = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising))
+ result |= MDIO_AN_T1_ADV_L_PAUSE_CAP;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising))
+ result |= MDIO_AN_T1_ADV_L_PAUSE_ASYM;
+
+ return result;
+}
+
+/**
+ * linkmode_adv_to_mii_t1_adv_m_t
+ * @advertising: the linkmode advertisement settings
+ *
+ * A small helper function that translates linkmode advertisement
+ * settings to phy autonegotiation advertisements for the
+ * BASE-T1 Autonegotiation Advertisement [31:16] Register.
+ */
+static inline u32 linkmode_adv_to_mii_t1_adv_m_t(unsigned long *advertising)
+{
+ u32 result = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, advertising))
+ result |= MDIO_AN_T1_ADV_M_B10L;
+
+ return result;
+}
+
int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 36ca2b5c2253..6c3048e2a3ce 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -698,6 +698,8 @@ struct phy_device {
u8 mdix;
u8 mdix_ctrl;
+ int pma_extable;
+
void (*phy_link_change)(struct phy_device *phydev, bool up);
void (*adjust_link)(struct net_device *dev);
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index fa3515257f54..75b7257a51e1 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -70,6 +70,7 @@
#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
+#define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
@@ -78,6 +79,7 @@
#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
+#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -170,6 +172,7 @@
#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
+#define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */
#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
@@ -223,6 +226,7 @@
#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
+#define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
/* PHY XGXS lane state register. */
@@ -301,6 +305,9 @@
#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
+/* BASE-T1 PMA/PMD extended ability register. */
+#define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */
+
/* BASE-T1 auto-negotiation advertisement register [15:0] */
#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
@@ -333,6 +340,9 @@
#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
+/* BASE-T1 PMA/PMD control register */
+#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */
+
/* EEE Supported/Advertisement/LP Advertisement registers.
*
* EEE capability Register (3.20), Advertisement (7.60) and
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (3 preceding siblings ...)
2022-03-24 11:26 ` [PATCH v5 4/7] net: phy: Add 10BASE-T1L support in phy-c45 alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-04-10 5:11 ` Ramon Fried
2022-03-24 11:26 ` [PATCH v5 6/7] net: phy: adin1100: Add SQI support alexandru.tachici
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt, Alexandru Ardelean
From: Alexandru Ardelean <alexandru.ardelean@analog.com>
The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
industrial Ethernet applications and is compliant with the IEEE 802.3cg
Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
drivers/net/phy/Kconfig | 7 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/adin1100.c | 247 +++++++++++++++++++++++++++++++++++++
3 files changed, 255 insertions(+)
create mode 100644 drivers/net/phy/adin1100.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index ea7571a2b39b..bbbf6c07ea53 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -83,6 +83,13 @@ config ADIN_PHY
- ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
Ethernet PHY
+config ADIN1100_PHY
+ tristate "Analog Devices Industrial Ethernet T1L PHYs"
+ help
+ Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
+ Currently supports the:
+ - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
+
config AQUANTIA_PHY
tristate "Aquantia PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index b2728d00fc9a..b82651b57043 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o
obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
+obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AMD_PHY) += amd.o
aquantia-objs += aquantia_main.o
ifdef CONFIG_HWMON
diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
new file mode 100644
index 000000000000..23d1ae61e0ef
--- /dev/null
+++ b/drivers/net/phy/adin1100.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Driver for Analog Devices Industrial Ethernet T1L PHYs
+ *
+ * Copyright 2020 Analog Devices Inc.
+ */
+#include <linux/kernel.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/phy.h>
+#include <linux/property.h>
+
+#define PHY_ID_ADIN1100 0x0283bc81
+
+#define ADIN_FORCED_MODE 0x8000
+#define ADIN_FORCED_MODE_EN BIT(0)
+
+#define ADIN_CRSM_SFT_RST 0x8810
+#define ADIN_CRSM_SFT_RST_EN BIT(0)
+
+#define ADIN_CRSM_SFT_PD_CNTRL 0x8812
+#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
+
+#define ADIN_AN_PHY_INST_STATUS 0x8030
+#define ADIN_IS_CFG_SLV BIT(2)
+#define ADIN_IS_CFG_MST BIT(3)
+
+#define ADIN_CRSM_STAT 0x8818
+#define ADIN_CRSM_SFT_PD_RDY BIT(1)
+#define ADIN_CRSM_SYS_RDY BIT(0)
+
+/**
+ * struct adin_priv - ADIN PHY driver private data
+ * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
+ * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)
+ * @tx_level_prop_present: set if the TX level is specified in DT
+ */
+struct adin_priv {
+ unsigned int tx_level_2v4_able:1;
+ unsigned int tx_level_2v4:1;
+ unsigned int tx_level_prop_present:1;
+};
+
+static int adin_read_status(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = genphy_c45_read_status(phydev);
+ if (ret)
+ return ret;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
+ if (ret < 0)
+ return ret;
+
+ if (ret & ADIN_IS_CFG_SLV)
+ phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
+
+ if (ret & ADIN_IS_CFG_MST)
+ phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
+
+ return 0;
+}
+
+static int adin_config_aneg(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ int ret;
+
+ if (phydev->autoneg == AUTONEG_DISABLE) {
+ ret = genphy_c45_pma_setup_forced(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (priv->tx_level_prop_present && priv->tx_level_2v4) {
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
+ MDIO_PMA_10T1L_CTRL_2V4_EN);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
+ MDIO_PMA_10T1L_CTRL_2V4_EN);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Force PHY to use above configurations */
+ return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
+ }
+
+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
+ if (ret < 0)
+ return ret;
+
+ /* Request increased transmit level from LP. */
+ if (priv->tx_level_prop_present && priv->tx_level_2v4) {
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
+ MDIO_AN_T1_ADV_H_10L_TX_HI |
+ MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Disable 2.4 Vpp transmit level. */
+ if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
+ ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
+ MDIO_AN_T1_ADV_H_10L_TX_HI |
+ MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
+ if (ret < 0)
+ return ret;
+ }
+
+ return genphy_c45_config_aneg(phydev);
+}
+
+static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
+{
+ int ret;
+ int val;
+
+ if (en)
+ val = ADIN_CRSM_SFT_PD_CNTRL_EN;
+ else
+ val = 0;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ ADIN_CRSM_SFT_PD_CNTRL, val);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
+ (ret & ADIN_CRSM_SFT_PD_RDY) == val,
+ 1000, 30000, true);
+}
+
+static int adin_suspend(struct phy_device *phydev)
+{
+ return adin_set_powerdown_mode(phydev, true);
+}
+
+static int adin_resume(struct phy_device *phydev)
+{
+ return adin_set_powerdown_mode(phydev, false);
+}
+
+static int adin_set_loopback(struct phy_device *phydev, bool enable)
+{
+ if (enable)
+ return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
+ BMCR_LOOPBACK);
+
+ /* PCS loopback (according to 10BASE-T1L spec) */
+ return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
+ BMCR_LOOPBACK);
+}
+
+static int adin_soft_reset(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
+ if (ret < 0)
+ return ret;
+
+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
+ (ret & ADIN_CRSM_SYS_RDY),
+ 10000, 30000, true);
+}
+
+static int adin_get_features(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+ int ret;
+ u8 val;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
+ if (ret < 0)
+ return ret;
+
+ /* This depends on the voltage level from the power source */
+ priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
+
+ phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
+ priv->tx_level_2v4_able ? "yes" : "no");
+
+ priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");
+ if (priv->tx_level_prop_present) {
+ ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);
+ if (ret < 0)
+ return ret;
+
+ priv->tx_level_2v4 = val;
+ if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
+ phydev_info(phydev,
+ "PHY supports 2.4V TX level, but disabled via config\n");
+ }
+
+ linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ return genphy_c45_pma_read_abilities(phydev);
+}
+
+static int adin_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct adin_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static struct phy_driver adin_driver[] = {
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),
+ .name = "ADIN1100",
+ .get_features = adin_get_features,
+ .soft_reset = adin_soft_reset,
+ .probe = adin_probe,
+ .config_aneg = adin_config_aneg,
+ .read_status = adin_read_status,
+ .set_loopback = adin_set_loopback,
+ .suspend = adin_suspend,
+ .resume = adin_resume,
+ },
+};
+
+module_phy_driver(adin_driver);
+
+static struct mdio_device_id __maybe_unused adin_tbl[] = {
+ { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, adin_tbl);
+MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
+MODULE_LICENSE("Dual BSD/GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-03-24 11:26 ` [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
@ 2022-04-10 5:11 ` Ramon Fried
2022-04-10 5:12 ` Ramon Fried
2022-04-12 0:17 ` Zhou Furong
0 siblings, 2 replies; 13+ messages in thread
From: Ramon Fried @ 2022-04-10 5:11 UTC (permalink / raw)
To: alexandru.tachici
Cc: andrew, o.rempel, davem, devicetree, hkallweit1, kuba, LKML,
linux, netdev, robh+dt, Alexandru Ardelean
On Fri, Mar 25, 2022 at 8:53 PM <alexandru.tachici@analog.com> wrote:
>
> From: Alexandru Ardelean <alexandru.ardelean@analog.com>
>
> The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
> industrial Ethernet applications and is compliant with the IEEE 802.3cg
> Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
> ---
> drivers/net/phy/Kconfig | 7 ++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/adin1100.c | 247 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 255 insertions(+)
> create mode 100644 drivers/net/phy/adin1100.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index ea7571a2b39b..bbbf6c07ea53 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -83,6 +83,13 @@ config ADIN_PHY
> - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
> Ethernet PHY
>
> +config ADIN1100_PHY
> + tristate "Analog Devices Industrial Ethernet T1L PHYs"
> + help
> + Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
> + Currently supports the:
> + - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
> +
> config AQUANTIA_PHY
> tristate "Aquantia PHYs"
> help
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index b2728d00fc9a..b82651b57043 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o
> obj-y += $(sfp-obj-y) $(sfp-obj-m)
>
> obj-$(CONFIG_ADIN_PHY) += adin.o
> +obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
> obj-$(CONFIG_AMD_PHY) += amd.o
> aquantia-objs += aquantia_main.o
> ifdef CONFIG_HWMON
> diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
> new file mode 100644
> index 000000000000..23d1ae61e0ef
> --- /dev/null
> +++ b/drivers/net/phy/adin1100.c
> @@ -0,0 +1,247 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Driver for Analog Devices Industrial Ethernet T1L PHYs
> + *
> + * Copyright 2020 Analog Devices Inc.
> + */
> +#include <linux/kernel.h>
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/phy.h>
> +#include <linux/property.h>
> +
> +#define PHY_ID_ADIN1100 0x0283bc81
> +
> +#define ADIN_FORCED_MODE 0x8000
> +#define ADIN_FORCED_MODE_EN BIT(0)
> +
> +#define ADIN_CRSM_SFT_RST 0x8810
> +#define ADIN_CRSM_SFT_RST_EN BIT(0)
> +
> +#define ADIN_CRSM_SFT_PD_CNTRL 0x8812
> +#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
> +
> +#define ADIN_AN_PHY_INST_STATUS 0x8030
> +#define ADIN_IS_CFG_SLV BIT(2)
> +#define ADIN_IS_CFG_MST BIT(3)
> +
> +#define ADIN_CRSM_STAT 0x8818
> +#define ADIN_CRSM_SFT_PD_RDY BIT(1)
> +#define ADIN_CRSM_SYS_RDY BIT(0)
> +
> +/**
> + * struct adin_priv - ADIN PHY driver private data
> + * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
> + * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)
> + * @tx_level_prop_present: set if the TX level is specified in DT
> + */
> +struct adin_priv {
> + unsigned int tx_level_2v4_able:1;
> + unsigned int tx_level_2v4:1;
> + unsigned int tx_level_prop_present:1;
> +};
> +
> +static int adin_read_status(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = genphy_c45_read_status(phydev);
> + if (ret)
> + return ret;
> +
> + ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
> + if (ret < 0)
> + return ret;
> +
> + if (ret & ADIN_IS_CFG_SLV)
> + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
> +
> + if (ret & ADIN_IS_CFG_MST)
> + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
> +
> + return 0;
> +}
> +
> +static int adin_config_aneg(struct phy_device *phydev)
> +{
> + struct adin_priv *priv = phydev->priv;
> + int ret;
> +
> + if (phydev->autoneg == AUTONEG_DISABLE) {
> + ret = genphy_c45_pma_setup_forced(phydev);
> + if (ret < 0)
> + return ret;
> +
> + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
> + MDIO_PMA_10T1L_CTRL_2V4_EN);
> + if (ret < 0)
> + return ret;
> + } else {
> + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
> + MDIO_PMA_10T1L_CTRL_2V4_EN);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Force PHY to use above configurations */
> + return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
> + }
> +
> + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
> + if (ret < 0)
> + return ret;
> +
> + /* Request increased transmit level from LP. */
> + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> + MDIO_AN_T1_ADV_H_10L_TX_HI |
> + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Disable 2.4 Vpp transmit level. */
> + if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
> + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> + MDIO_AN_T1_ADV_H_10L_TX_HI |
> + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return genphy_c45_config_aneg(phydev);
> +}
> +
> +static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
> +{
> + int ret;
> + int val;
> +
> + if (en)
> + val = ADIN_CRSM_SFT_PD_CNTRL_EN;
> + else
> + val = 0;
> +
> + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
> + ADIN_CRSM_SFT_PD_CNTRL, val);
> + if (ret < 0)
> + return ret;
> +
> + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> + (ret & ADIN_CRSM_SFT_PD_RDY) == val,
> + 1000, 30000, true);
> +}
> +
> +static int adin_suspend(struct phy_device *phydev)
> +{
> + return adin_set_powerdown_mode(phydev, true);
> +}
> +
> +static int adin_resume(struct phy_device *phydev)
> +{
> + return adin_set_powerdown_mode(phydev, false);
> +}
> +
> +static int adin_set_loopback(struct phy_device *phydev, bool enable)
> +{
> + if (enable)
> + return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> + BMCR_LOOPBACK);
> +
> + /* PCS loopback (according to 10BASE-T1L spec) */
> + return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> + BMCR_LOOPBACK);
> +}
> +
> +static int adin_soft_reset(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
> + if (ret < 0)
> + return ret;
> +
> + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> + (ret & ADIN_CRSM_SYS_RDY),
> + 10000, 30000, true);
> +}
> +
> +static int adin_get_features(struct phy_device *phydev)
> +{
> + struct adin_priv *priv = phydev->priv;
> + struct device *dev = &phydev->mdio.dev;
> + int ret;
> + u8 val;
> +
> + ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
> + if (ret < 0)
> + return ret;
> +
> + /* This depends on the voltage level from the power source */
> + priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
> +
> + phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
> + priv->tx_level_2v4_able ? "yes" : "no");
> +
> + priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");
> + if (priv->tx_level_prop_present) {
> + ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);
> + if (ret < 0)
> + return ret;
> +
> + priv->tx_level_2v4 = val;
> + if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
> + phydev_info(phydev,
> + "PHY supports 2.4V TX level, but disabled via config\n");
> + }
> +
> + linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
> + phydev->supported);
> +
> + return genphy_c45_pma_read_abilities(phydev);
> +}
> +
> +static int adin_probe(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + struct adin_priv *priv;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + phydev->priv = priv;
> +
> + return 0;
> +}
> +
> +static struct phy_driver adin_driver[] = {
> + {
> + PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),
> + .name = "ADIN1100",
> + .get_features = adin_get_features,
> + .soft_reset = adin_soft_reset,
> + .probe = adin_probe,
> + .config_aneg = adin_config_aneg,
> + .read_status = adin_read_status,
> + .set_loopback = adin_set_loopback,
> + .suspend = adin_suspend,
> + .resume = adin_resume,
> + },
> +};
> +
> +module_phy_driver(adin_driver);
> +
> +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(mdio, adin_tbl);
> +MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
> +MODULE_LICENSE("Dual BSD/GPL");
> --
> 2.25.1
>
Hi.
Got two submissions for both drivers in parallel.
https://patchwork.ozlabs.org/project/uboot/patch/20220408162814.227120-1-nate.d@variscite.com/
are you aware of each other ?
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-04-10 5:11 ` Ramon Fried
@ 2022-04-10 5:12 ` Ramon Fried
2022-04-12 0:17 ` Zhou Furong
1 sibling, 0 replies; 13+ messages in thread
From: Ramon Fried @ 2022-04-10 5:12 UTC (permalink / raw)
To: alexandru.tachici
Cc: andrew, o.rempel, davem, devicetree, hkallweit1, kuba, LKML,
linux, netdev, robh+dt, Alexandru Ardelean
On Sun, Apr 10, 2022 at 8:11 AM Ramon Fried <rfried.dev@gmail.com> wrote:
>
> On Fri, Mar 25, 2022 at 8:53 PM <alexandru.tachici@analog.com> wrote:
> >
> > From: Alexandru Ardelean <alexandru.ardelean@analog.com>
> >
> > The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
> > industrial Ethernet applications and is compliant with the IEEE 802.3cg
> > Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
> > ---
> > drivers/net/phy/Kconfig | 7 ++
> > drivers/net/phy/Makefile | 1 +
> > drivers/net/phy/adin1100.c | 247 +++++++++++++++++++++++++++++++++++++
> > 3 files changed, 255 insertions(+)
> > create mode 100644 drivers/net/phy/adin1100.c
> >
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index ea7571a2b39b..bbbf6c07ea53 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -83,6 +83,13 @@ config ADIN_PHY
> > - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
> > Ethernet PHY
> >
> > +config ADIN1100_PHY
> > + tristate "Analog Devices Industrial Ethernet T1L PHYs"
> > + help
> > + Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
> > + Currently supports the:
> > + - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
> > +
> > config AQUANTIA_PHY
> > tristate "Aquantia PHYs"
> > help
> > diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> > index b2728d00fc9a..b82651b57043 100644
> > --- a/drivers/net/phy/Makefile
> > +++ b/drivers/net/phy/Makefile
> > @@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o
> > obj-y += $(sfp-obj-y) $(sfp-obj-m)
> >
> > obj-$(CONFIG_ADIN_PHY) += adin.o
> > +obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
> > obj-$(CONFIG_AMD_PHY) += amd.o
> > aquantia-objs += aquantia_main.o
> > ifdef CONFIG_HWMON
> > diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
> > new file mode 100644
> > index 000000000000..23d1ae61e0ef
> > --- /dev/null
> > +++ b/drivers/net/phy/adin1100.c
> > @@ -0,0 +1,247 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +/*
> > + * Driver for Analog Devices Industrial Ethernet T1L PHYs
> > + *
> > + * Copyright 2020 Analog Devices Inc.
> > + */
> > +#include <linux/kernel.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/delay.h>
> > +#include <linux/errno.h>
> > +#include <linux/init.h>
> > +#include <linux/module.h>
> > +#include <linux/mii.h>
> > +#include <linux/phy.h>
> > +#include <linux/property.h>
> > +
> > +#define PHY_ID_ADIN1100 0x0283bc81
> > +
> > +#define ADIN_FORCED_MODE 0x8000
> > +#define ADIN_FORCED_MODE_EN BIT(0)
> > +
> > +#define ADIN_CRSM_SFT_RST 0x8810
> > +#define ADIN_CRSM_SFT_RST_EN BIT(0)
> > +
> > +#define ADIN_CRSM_SFT_PD_CNTRL 0x8812
> > +#define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
> > +
> > +#define ADIN_AN_PHY_INST_STATUS 0x8030
> > +#define ADIN_IS_CFG_SLV BIT(2)
> > +#define ADIN_IS_CFG_MST BIT(3)
> > +
> > +#define ADIN_CRSM_STAT 0x8818
> > +#define ADIN_CRSM_SFT_PD_RDY BIT(1)
> > +#define ADIN_CRSM_SYS_RDY BIT(0)
> > +
> > +/**
> > + * struct adin_priv - ADIN PHY driver private data
> > + * @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
> > + * @tx_level_2v4: set if the PHY requests 2.4V TX levels (10BASE-T1L)
> > + * @tx_level_prop_present: set if the TX level is specified in DT
> > + */
> > +struct adin_priv {
> > + unsigned int tx_level_2v4_able:1;
> > + unsigned int tx_level_2v4:1;
> > + unsigned int tx_level_prop_present:1;
> > +};
> > +
> > +static int adin_read_status(struct phy_device *phydev)
> > +{
> > + int ret;
> > +
> > + ret = genphy_c45_read_status(phydev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (ret & ADIN_IS_CFG_SLV)
> > + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
> > +
> > + if (ret & ADIN_IS_CFG_MST)
> > + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
> > +
> > + return 0;
> > +}
> > +
> > +static int adin_config_aneg(struct phy_device *phydev)
> > +{
> > + struct adin_priv *priv = phydev->priv;
> > + int ret;
> > +
> > + if (phydev->autoneg == AUTONEG_DISABLE) {
> > + ret = genphy_c45_pma_setup_forced(phydev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
> > + ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
> > + MDIO_PMA_10T1L_CTRL_2V4_EN);
> > + if (ret < 0)
> > + return ret;
> > + } else {
> > + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
> > + MDIO_PMA_10T1L_CTRL_2V4_EN);
> > + if (ret < 0)
> > + return ret;
> > + }
> > +
> > + /* Force PHY to use above configurations */
> > + return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
> > + }
> > +
> > + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* Request increased transmit level from LP. */
> > + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
> > + ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> > + MDIO_AN_T1_ADV_H_10L_TX_HI |
> > + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> > + if (ret < 0)
> > + return ret;
> > + }
> > +
> > + /* Disable 2.4 Vpp transmit level. */
> > + if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {
> > + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
> > + MDIO_AN_T1_ADV_H_10L_TX_HI |
> > + MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);
> > + if (ret < 0)
> > + return ret;
> > + }
> > +
> > + return genphy_c45_config_aneg(phydev);
> > +}
> > +
> > +static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
> > +{
> > + int ret;
> > + int val;
> > +
> > + if (en)
> > + val = ADIN_CRSM_SFT_PD_CNTRL_EN;
> > + else
> > + val = 0;
> > +
> > + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
> > + ADIN_CRSM_SFT_PD_CNTRL, val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> > + (ret & ADIN_CRSM_SFT_PD_RDY) == val,
> > + 1000, 30000, true);
> > +}
> > +
> > +static int adin_suspend(struct phy_device *phydev)
> > +{
> > + return adin_set_powerdown_mode(phydev, true);
> > +}
> > +
> > +static int adin_resume(struct phy_device *phydev)
> > +{
> > + return adin_set_powerdown_mode(phydev, false);
> > +}
> > +
> > +static int adin_set_loopback(struct phy_device *phydev, bool enable)
> > +{
> > + if (enable)
> > + return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> > + BMCR_LOOPBACK);
> > +
> > + /* PCS loopback (according to 10BASE-T1L spec) */
> > + return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
> > + BMCR_LOOPBACK);
> > +}
> > +
> > +static int adin_soft_reset(struct phy_device *phydev)
> > +{
> > + int ret;
> > +
> > + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
> > + (ret & ADIN_CRSM_SYS_RDY),
> > + 10000, 30000, true);
> > +}
> > +
> > +static int adin_get_features(struct phy_device *phydev)
> > +{
> > + struct adin_priv *priv = phydev->priv;
> > + struct device *dev = &phydev->mdio.dev;
> > + int ret;
> > + u8 val;
> > +
> > + ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* This depends on the voltage level from the power source */
> > + priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
> > +
> > + phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",
> > + priv->tx_level_2v4_able ? "yes" : "no");
> > +
> > + priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");
> > + if (priv->tx_level_prop_present) {
> > + ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv->tx_level_2v4 = val;
> > + if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)
> > + phydev_info(phydev,
> > + "PHY supports 2.4V TX level, but disabled via config\n");
> > + }
> > +
> > + linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),
> > + phydev->supported);
> > +
> > + return genphy_c45_pma_read_abilities(phydev);
> > +}
> > +
> > +static int adin_probe(struct phy_device *phydev)
> > +{
> > + struct device *dev = &phydev->mdio.dev;
> > + struct adin_priv *priv;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + phydev->priv = priv;
> > +
> > + return 0;
> > +}
> > +
> > +static struct phy_driver adin_driver[] = {
> > + {
> > + PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),
> > + .name = "ADIN1100",
> > + .get_features = adin_get_features,
> > + .soft_reset = adin_soft_reset,
> > + .probe = adin_probe,
> > + .config_aneg = adin_config_aneg,
> > + .read_status = adin_read_status,
> > + .set_loopback = adin_set_loopback,
> > + .suspend = adin_suspend,
> > + .resume = adin_resume,
> > + },
> > +};
> > +
> > +module_phy_driver(adin_driver);
> > +
> > +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> > + { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
> > + { }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(mdio, adin_tbl);
> > +MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");
> > +MODULE_LICENSE("Dual BSD/GPL");
> > --
> > 2.25.1
> >
> Hi.
> Got two submissions for both drivers in parallel.
> https://patchwork.ozlabs.org/project/uboot/patch/20220408162814.227120-1-nate.d@variscite.com/
> are you aware of each other ?
Ignore last mail. I should go to sleep....
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-04-10 5:11 ` Ramon Fried
2022-04-10 5:12 ` Ramon Fried
@ 2022-04-12 0:17 ` Zhou Furong
1 sibling, 0 replies; 13+ messages in thread
From: Zhou Furong @ 2022-04-12 0:17 UTC (permalink / raw)
To: alexandru.tachici
Cc: andrew, o.rempel, davem, devicetree, hkallweit1, kuba, LKML,
linux, netdev, robh+dt, Alexandru Ardelean, Ramon Fried
Hi,
>> +static int adin_config_aneg(struct phy_device *phydev)
>> +{
>> + struct adin_priv *priv = phydev->priv;
>> + int ret;
>> +
>> + if (phydev->autoneg == AUTONEG_DISABLE) {
>> + ret = genphy_c45_pma_setup_forced(phydev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (priv->tx_level_prop_present && priv->tx_level_2v4) {
>> + ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
>> + MDIO_PMA_10T1L_CTRL_2V4_EN);
>> + if (ret < 0)
>> + return ret;
>> + } else {
>> + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
>> + MDIO_PMA_10T1L_CTRL_2V4_EN);
>> + if (ret < 0)
>> + return ret;
>> + }
move below out if/else
if(ret < 0)
return ret;
>> +static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)
>> +{
>> + int ret;
>> + int val;
>> +
>> + if (en)
>> + val = ADIN_CRSM_SFT_PD_CNTRL_EN;
>> + else
>> + val = 0;please consider below change which looks neat
val = en? ADIN_CRSM_SFT_PD_CNTRL_EN : 0
Best regards,
Furong
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 6/7] net: phy: adin1100: Add SQI support
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (4 preceding siblings ...)
2022-03-24 11:26 ` [PATCH v5 5/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 11:26 ` [PATCH v5 7/7] dt-bindings: net: phy: Add 10-baseT1L 2.4 Vpp alexandru.tachici
2022-03-24 23:00 ` [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY Jakub Kicinski
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
Determine the SQI from MSE using a predefined table
for the 10BASE-T1L.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
drivers/net/phy/adin1100.c | 52 ++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/net/phy/adin1100.c b/drivers/net/phy/adin1100.c
index 23d1ae61e0ef..9cbe8b92dc6f 100644
--- a/drivers/net/phy/adin1100.c
+++ b/drivers/net/phy/adin1100.c
@@ -33,6 +33,26 @@
#define ADIN_CRSM_SFT_PD_RDY BIT(1)
#define ADIN_CRSM_SYS_RDY BIT(0)
+#define ADIN_MSE_VAL 0x830B
+
+#define ADIN_SQI_MAX 7
+
+struct adin_mse_sqi_range {
+ u16 start;
+ u16 end;
+};
+
+static const struct adin_mse_sqi_range adin_mse_sqi_map[] = {
+ { 0x0A74, 0xFFFF },
+ { 0x084E, 0x0A74 },
+ { 0x0698, 0x084E },
+ { 0x053D, 0x0698 },
+ { 0x0429, 0x053D },
+ { 0x034E, 0x0429 },
+ { 0x02A0, 0x034E },
+ { 0x0000, 0x02A0 },
+};
+
/**
* struct adin_priv - ADIN PHY driver private data
* @tx_level_2v4_able: set if the PHY supports 2.4V TX levels (10BASE-T1L)
@@ -206,6 +226,36 @@ static int adin_get_features(struct phy_device *phydev)
return genphy_c45_pma_read_abilities(phydev);
}
+static int adin_get_sqi(struct phy_device *phydev)
+{
+ u16 mse_val;
+ int sqi;
+ int ret;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
+ if (ret < 0)
+ return ret;
+ else if (!(ret & MDIO_STAT1_LSTATUS))
+ return 0;
+
+ ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);
+ if (ret < 0)
+ return ret;
+
+ mse_val = 0xFFFF & ret;
+ for (sqi = 0; sqi < ARRAY_SIZE(adin_mse_sqi_map); sqi++) {
+ if (mse_val >= adin_mse_sqi_map[sqi].start && mse_val <= adin_mse_sqi_map[sqi].end)
+ return sqi;
+ }
+
+ return -EINVAL;
+}
+
+static int adin_get_sqi_max(struct phy_device *phydev)
+{
+ return ADIN_SQI_MAX;
+}
+
static int adin_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -232,6 +282,8 @@ static struct phy_driver adin_driver[] = {
.set_loopback = adin_set_loopback,
.suspend = adin_suspend,
.resume = adin_resume,
+ .get_sqi = adin_get_sqi,
+ .get_sqi_max = adin_get_sqi_max,
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 7/7] dt-bindings: net: phy: Add 10-baseT1L 2.4 Vpp
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (5 preceding siblings ...)
2022-03-24 11:26 ` [PATCH v5 6/7] net: phy: adin1100: Add SQI support alexandru.tachici
@ 2022-03-24 11:26 ` alexandru.tachici
2022-03-24 23:00 ` [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY Jakub Kicinski
7 siblings, 0 replies; 13+ messages in thread
From: alexandru.tachici @ 2022-03-24 11:26 UTC (permalink / raw)
To: andrew
Cc: o.rempel, alexandru.tachici, davem, devicetree, hkallweit1, kuba,
linux-kernel, linux, netdev, robh+dt
From: Alexandru Tachici <alexandru.tachici@analog.com>
Add a tristate property to advertise desired transmit level.
If the device supports the 2.4 Vpp operating mode for 10BASE-T1L,
as defined in 802.3gc, and the 2.4 Vpp transmit voltage operation
is desired, property should be set to 1. This property is used
to select whether Auto-Negotiation advertises a request to
operate the 10BASE-T1L PHY in increased transmit level mode.
If property is set to 1, the PHY shall advertise a request
to operate the 10BASE-T1L PHY in increased transmit level mode.
If property is set to zero, the PHY shall not advertise
a request to operate the 10BASE-T1L PHY in increased transmit level mode.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
Documentation/devicetree/bindings/net/ethernet-phy.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index ee42328a109d..ed1415a4381f 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -77,6 +77,15 @@ properties:
description:
Maximum PHY supported speed in Mbits / seconds.
+ phy-10base-t1l-2.4vpp:
+ description: |
+ tristate, request/disable 2.4 Vpp operating mode. The values are:
+ 0: Disable 2.4 Vpp operating mode.
+ 1: Request 2.4 Vpp operating mode from link partner.
+ Absence of this property will leave configuration to default values.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [0, 1]
+
broken-turn-around:
$ref: /schemas/types.yaml#/definitions/flag
description:
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-03-24 11:26 [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY alexandru.tachici
` (6 preceding siblings ...)
2022-03-24 11:26 ` [PATCH v5 7/7] dt-bindings: net: phy: Add 10-baseT1L 2.4 Vpp alexandru.tachici
@ 2022-03-24 23:00 ` Jakub Kicinski
2022-04-07 12:05 ` Oleksij Rempel
7 siblings, 1 reply; 13+ messages in thread
From: Jakub Kicinski @ 2022-03-24 23:00 UTC (permalink / raw)
To: alexandru.tachici
Cc: andrew, o.rempel, davem, devicetree, hkallweit1, linux-kernel,
linux, netdev, robh+dt
On Thu, 24 Mar 2022 13:26:13 +0200 alexandru.tachici@analog.com wrote:
> The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
> industrial Ethernet applications and is compliant with the IEEE 802.3cg
> Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
# Form letter - net-next is closed
We have already sent the networking pull request for 5.18
and therefore net-next is closed for new drivers, features,
code refactoring and optimizations. We are currently accepting
bug fixes only.
Please repost when net-next reopens after 5.18-rc1 is cut.
RFC patches sent for review only are obviously welcome at any time.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY
2022-03-24 23:00 ` [PATCH v5 0/7] net: phy: adin1100: Add initial support for ADIN1100 industrial PHY Jakub Kicinski
@ 2022-04-07 12:05 ` Oleksij Rempel
0 siblings, 0 replies; 13+ messages in thread
From: Oleksij Rempel @ 2022-04-07 12:05 UTC (permalink / raw)
To: Jakub Kicinski
Cc: alexandru.tachici, andrew, davem, devicetree, hkallweit1,
linux-kernel, linux, netdev, robh+dt, kernel
On Thu, Mar 24, 2022 at 04:00:41PM -0700, Jakub Kicinski wrote:
> On Thu, 24 Mar 2022 13:26:13 +0200 alexandru.tachici@analog.com wrote:
> > The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
> > industrial Ethernet applications and is compliant with the IEEE 802.3cg
> > Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.
>
> # Form letter - net-next is closed
>
> We have already sent the networking pull request for 5.18
> and therefore net-next is closed for new drivers, features,
> code refactoring and optimizations. We are currently accepting
> bug fixes only.
>
> Please repost when net-next reopens after 5.18-rc1 is cut.
>
> RFC patches sent for review only are obviously welcome at any time.
Hi Alexandru net-next is open now, you can rebase and resend this
patches.
Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 13+ messages in thread