* [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs
@ 2022-03-20 9:59 Chuanhong Guo
2022-03-20 9:59 ` [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG Chuanhong Guo
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 9:59 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
This patchset adds support for gigadevice SPI NANDs currently
in production.
Tested the following chip by reading and writing a large file on
UBIFS:
GD5F1GQ5UEYIG
GD5F2GQ5UEYIG
GD5F4GQ6UEYIG
GD5F2GM7UEYIG
GD5F4GM8UEYIG
Other untested ones are variants of tested or currently
supported chips with different voltage and capacity.
Chuanhong Guo (5):
mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG
mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG
mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG
mtd: spinand: gigadevice: add support for GD5FxGM7xExxG
drivers/mtd/nand/spi/gigadevice.c | 158 +++++++++++++++++++++++++++++-
1 file changed, 157 insertions(+), 1 deletion(-)
--
2.35.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
@ 2022-03-20 9:59 ` Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 9:59 ` [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG Chuanhong Guo
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 9:59 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
Read From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according
to page 23 of the datasheet[0].
[0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/
Fixes: 469b99248985 ("mtd: spinand: gigadevice: Support GD5F1GQ5UExxG")
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 1dd1c5898093..da77ab20296e 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -39,6 +39,14 @@ static SPINAND_OP_VARIANTS(read_cache_variants_f,
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -339,7 +347,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
2022-03-20 9:59 ` [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG Chuanhong Guo
@ 2022-03-20 9:59 ` Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 9:59 ` [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG Chuanhong Guo
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 9:59 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
Add support for:
GD5F1GQ4RExxG
GD5F2GQ4{U,R}ExxG
These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
and capacity.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index da77ab20296e..85a61d3d8467 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -333,6 +333,36 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UFxxG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
2022-03-20 9:59 ` [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG Chuanhong Guo
2022-03-20 9:59 ` [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG Chuanhong Guo
@ 2022-03-20 9:59 ` Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 10:00 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG Chuanhong Guo
2022-03-20 10:00 ` [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG Chuanhong Guo
4 siblings, 1 reply; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 9:59 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
This chip is the 1.8v version of GD5F1GQ5UExxG.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 85a61d3d8467..d519bb85f0e7 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -383,6 +383,16 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
` (2 preceding siblings ...)
2022-03-20 9:59 ` [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG Chuanhong Guo
@ 2022-03-20 10:00 ` Chuanhong Guo
2022-04-04 8:47 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2, 4}GQ5xExxG Miquel Raynal
2022-03-20 10:00 ` [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG Chuanhong Guo
4 siblings, 1 reply; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 10:00 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
Add support for:
GD5F2GQ5{U,R}ExxG
GD5F4GQ6{U,R}ExxG
These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.
Besides that and memory layout, they are identical to their 1G variant.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index d519bb85f0e7..fcd1c4e474a2 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -393,6 +401,46 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
` (3 preceding siblings ...)
2022-03-20 10:00 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG Chuanhong Guo
@ 2022-03-20 10:00 ` Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
4 siblings, 1 reply; 11+ messages in thread
From: Chuanhong Guo @ 2022-03-20 10:00 UTC (permalink / raw)
To: linux-mtd
Cc: Chuanhong Guo, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Reto Schneider, Frieder Schrempf,
Stefan Roese, open list
Add support for:
GD5F{1,2}GM7{U,R}ExxG
GD5F4GM8{U,R}ExxG
These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
with 8b/512b on-die ECC capability.
These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
instruction for reading page cache. It isn't added in this patch because
I don't have a DTR spi controller for testing.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index fcd1c4e474a2..6b043e24855f 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -441,6 +441,66 @@ static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
};
static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG
2022-03-20 10:00 ` [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG Chuanhong Guo
@ 2022-04-04 8:47 ` Miquel Raynal
0 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2022-04-04 8:47 UTC (permalink / raw)
To: Chuanhong Guo, linux-mtd
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Reto Schneider, Frieder Schrempf, Stefan Roese, open list
On Sun, 2022-03-20 at 10:00:01 UTC, Chuanhong Guo wrote:
> Add support for:
> GD5F{1,2}GM7{U,R}ExxG
> GD5F4GM8{U,R}ExxG
>
> These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
> with 8b/512b on-die ECC capability.
> These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
> instruction for reading page cache. It isn't added in this patch because
> I don't have a DTR spi controller for testing.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2, 4}GQ5xExxG
2022-03-20 10:00 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG Chuanhong Guo
@ 2022-04-04 8:47 ` Miquel Raynal
0 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2022-04-04 8:47 UTC (permalink / raw)
To: Chuanhong Guo, linux-mtd
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Reto Schneider, Frieder Schrempf, Stefan Roese, open list
On Sun, 2022-03-20 at 10:00:00 UTC, Chuanhong Guo wrote:
> Add support for:
> GD5F2GQ5{U,R}ExxG
> GD5F4GQ6{U,R}ExxG
>
> These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.
> Besides that and memory layout, they are identical to their 1G variant.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG
2022-03-20 9:59 ` [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG Chuanhong Guo
@ 2022-04-04 8:47 ` Miquel Raynal
0 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2022-04-04 8:47 UTC (permalink / raw)
To: Chuanhong Guo, linux-mtd
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Reto Schneider, Frieder Schrempf, Stefan Roese, open list
On Sun, 2022-03-20 at 09:59:59 UTC, Chuanhong Guo wrote:
> This chip is the 1.8v version of GD5F1GQ5UExxG.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
2022-03-20 9:59 ` [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG Chuanhong Guo
@ 2022-04-04 8:47 ` Miquel Raynal
0 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2022-04-04 8:47 UTC (permalink / raw)
To: Chuanhong Guo, linux-mtd
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Reto Schneider, Frieder Schrempf, Stefan Roese, open list
On Sun, 2022-03-20 at 09:59:58 UTC, Chuanhong Guo wrote:
> Add support for:
> GD5F1GQ4RExxG
> GD5F2GQ4{U,R}ExxG
>
> These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
> and capacity.
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG
2022-03-20 9:59 ` [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG Chuanhong Guo
@ 2022-04-04 8:47 ` Miquel Raynal
0 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2022-04-04 8:47 UTC (permalink / raw)
To: Chuanhong Guo, linux-mtd
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Reto Schneider, Frieder Schrempf, Stefan Roese, open list
On Sun, 2022-03-20 at 09:59:57 UTC, Chuanhong Guo wrote:
> Read From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according
> to page 23 of the datasheet[0].
>
> [0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/
>
> Fixes: 469b99248985 ("mtd: spinand: gigadevice: Support GD5F1GQ5UExxG")
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-04-04 8:47 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-20 9:59 [PATCH 0/5] mtd: spinand: add support for more GD SPI NANDs Chuanhong Guo
2022-03-20 9:59 ` [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 9:59 ` [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 9:59 ` [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
2022-03-20 10:00 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,4}GQ5xExxG Chuanhong Guo
2022-04-04 8:47 ` [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2, 4}GQ5xExxG Miquel Raynal
2022-03-20 10:00 ` [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG Chuanhong Guo
2022-04-04 8:47 ` Miquel Raynal
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