* [PATCH] arm64: dts: qcom: db845c: Add support for MCP2517FD
@ 2022-04-18 12:58 Vinod Koul
2022-04-18 13:42 ` Manivannan Sadhasivam
0 siblings, 1 reply; 3+ messages in thread
From: Vinod Koul @ 2022-04-18 12:58 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel, Manivannan Sadhasivam
Add support for onboard MCP2517FD SPI CAN transceiver attached to
SPI0 of RB3.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 28fe45c5d516..5179f8ddb060 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -28,6 +28,13 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ /* Fixed crystal oscillator dedicated to MCP2517FD */
+ clk40M: can_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ };
+
dc12v: dc12v-regulator {
compatible = "regulator-fixed";
regulator-name = "DC12V";
@@ -746,6 +753,22 @@ codec {
};
};
+&spi0 {
+ /* On Low speed expansion */
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2517fd";
+ reg = <0>;
+ clocks = <&clk40M>;
+ interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&vdc_5v>;
+ xceiver-supply = <&vdc_5v>;
+ status = "okay";
+ };
+};
+
&spi2 {
/* On Low speed expansion */
label = "LS-SPI0";
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: qcom: db845c: Add support for MCP2517FD
2022-04-18 12:58 [PATCH] arm64: dts: qcom: db845c: Add support for MCP2517FD Vinod Koul
@ 2022-04-18 13:42 ` Manivannan Sadhasivam
2022-04-19 3:35 ` Vinod Koul
0 siblings, 1 reply; 3+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-18 13:42 UTC (permalink / raw)
To: Vinod Koul
Cc: Bjorn Andersson, linux-arm-msm, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel
On Mon, Apr 18, 2022 at 06:28:41PM +0530, Vinod Koul wrote:
> Add support for onboard MCP2517FD SPI CAN transceiver attached to
> SPI0 of RB3.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> index 28fe45c5d516..5179f8ddb060 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> @@ -28,6 +28,13 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + /* Fixed crystal oscillator dedicated to MCP2517FD */
> + clk40M: can_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <40000000>;
> + };
> +
> dc12v: dc12v-regulator {
> compatible = "regulator-fixed";
> regulator-name = "DC12V";
> @@ -746,6 +753,22 @@ codec {
> };
> };
>
> +&spi0 {
> + /* On Low speed expansion */
Only SPI2 is exposed on the LS header. This one is dedicated to CAN controller.
> + status = "okay";
No chip select? Since CAN controller may operate at higher frequencies, it
makes sense to increase the drive strength of the pins.
Thanks,
Mani
> +
> + can@0 {
> + compatible = "microchip,mcp2517fd";
> + reg = <0>;
> + clocks = <&clk40M>;
> + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> + spi-max-frequency = <10000000>;
> + vdd-supply = <&vdc_5v>;
> + xceiver-supply = <&vdc_5v>;
> + status = "okay";
> + };
> +};
> +
> &spi2 {
> /* On Low speed expansion */
> label = "LS-SPI0";
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: qcom: db845c: Add support for MCP2517FD
2022-04-18 13:42 ` Manivannan Sadhasivam
@ 2022-04-19 3:35 ` Vinod Koul
0 siblings, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2022-04-19 3:35 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Bjorn Andersson, linux-arm-msm, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel
On 18-04-22, 19:12, Manivannan Sadhasivam wrote:
> On Mon, Apr 18, 2022 at 06:28:41PM +0530, Vinod Koul wrote:
> > Add support for onboard MCP2517FD SPI CAN transceiver attached to
> > SPI0 of RB3.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 23 ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> > index 28fe45c5d516..5179f8ddb060 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> > +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
> > @@ -28,6 +28,13 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + /* Fixed crystal oscillator dedicated to MCP2517FD */
> > + clk40M: can_clock {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <40000000>;
> > + };
> > +
> > dc12v: dc12v-regulator {
> > compatible = "regulator-fixed";
> > regulator-name = "DC12V";
> > @@ -746,6 +753,22 @@ codec {
> > };
> > };
> >
> > +&spi0 {
> > + /* On Low speed expansion */
>
> Only SPI2 is exposed on the LS header. This one is dedicated to CAN controller.
ok
>
> > + status = "okay";
>
> No chip select? Since CAN controller may operate at higher frequencies, it
> makes sense to increase the drive strength of the pins.
Okay will add and send v2
--
~Vinod
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-04-19 3:36 UTC | newest]
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2022-04-18 12:58 [PATCH] arm64: dts: qcom: db845c: Add support for MCP2517FD Vinod Koul
2022-04-18 13:42 ` Manivannan Sadhasivam
2022-04-19 3:35 ` Vinod Koul
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