* [PATCH 1/4] arm: dts: mediatek: Get rid of mediatek,larb for MM nodes
2022-04-21 3:51 [PATCH 0/4] Correct power domain for encoder Allen-KH Cheng
@ 2022-04-21 3:51 ` Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 2/4] arm64: " Allen-KH Cheng
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Allen-KH Cheng @ 2022-04-21 3:51 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Yong Wu, Allen-KH Cheng
From: Yong Wu <yong.wu@mediatek.com>
After adding device_link between the IOMMU consumer and smi, the
mediatek,larb is unnecessary now.
CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Tested-by: Frank Wunderlich <frank-w@public-files.de> # BPI-R2/MT7623
---
arch/arm/boot/dts/mt2701.dtsi | 2 --
arch/arm/boot/dts/mt7623n.dtsi | 5 -----
2 files changed, 7 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4776f85d6d5b..ef583cfd3baf 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -564,7 +564,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
@@ -577,7 +576,6 @@
clocks = <&imgsys CLK_IMG_VENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
};
diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
index bcb0846e29fd..3adab5cd1fef 100644
--- a/arch/arm/boot/dts/mt7623n.dtsi
+++ b/arch/arm/boot/dts/mt7623n.dtsi
@@ -121,7 +121,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
@@ -144,7 +143,6 @@
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_OVL>;
iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
- mediatek,larb = <&larb0>;
};
rdma0: rdma@14008000 {
@@ -154,7 +152,6 @@
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
- mediatek,larb = <&larb0>;
};
wdma@14009000 {
@@ -164,7 +161,6 @@
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_WDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
- mediatek,larb = <&larb0>;
};
bls: pwm@1400a000 {
@@ -215,7 +211,6 @@
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb0>;
};
dpi0: dpi@14014000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/4] arm64: dts: mediatek: Get rid of mediatek,larb for MM nodes
2022-04-21 3:51 [PATCH 0/4] Correct power domain for encoder Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 1/4] arm: dts: mediatek: Get rid of mediatek,larb for MM nodes Allen-KH Cheng
@ 2022-04-21 3:51 ` Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 3/4] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes Allen-KH Cheng
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Allen-KH Cheng @ 2022-04-21 3:51 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Yong Wu, Allen-KH Cheng
From: Yong Wu <yong.wu@mediatek.com>
After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.
CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ----------------
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------
2 files changed, 22 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 848e3f39c8ef..10291b2690ab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1010,7 +1010,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -1021,7 +1020,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -1051,7 +1049,6 @@
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -1060,7 +1057,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -1069,7 +1065,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
};
ovl0: ovl@1400c000 {
@@ -1079,7 +1074,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1090,7 +1084,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
@@ -1101,7 +1094,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
@@ -1112,7 +1104,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
@@ -1123,7 +1114,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
@@ -1134,7 +1124,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
@@ -1145,7 +1134,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
@@ -1399,7 +1387,6 @@
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1467,7 +1454,6 @@
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1495,7 +1481,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
<&iommu M4U_PORT_JPGDEC_BSDMA>;
};
@@ -1529,7 +1514,6 @@
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index d1448a0b86cb..be9728526ed3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1396,7 +1396,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
@@ -1407,7 +1406,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
@@ -1418,7 +1416,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
@@ -1429,7 +1426,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
@@ -1441,7 +1437,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1598,7 +1593,6 @@
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb4>;
iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
<&iommu M4U_PORT_JPGENC_BSDMA>;
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/4] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
2022-04-21 3:51 [PATCH 0/4] Correct power domain for encoder Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 1/4] arm: dts: mediatek: Get rid of mediatek,larb for MM nodes Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 2/4] arm64: " Allen-KH Cheng
@ 2022-04-21 3:51 ` Allen-KH Cheng
2022-04-21 3:51 ` [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property Allen-KH Cheng
2022-04-22 13:49 ` [PATCH 0/4] Correct power domain for encoder Matthias Brugger
4 siblings, 0 replies; 8+ messages in thread
From: Allen-KH Cheng @ 2022-04-21 3:51 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng, Irui Wang
The power of encoder is not control by mediatek,larb, so we add
power domain to encoder nodes for mt8173 SoC.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 10291b2690ab..eebc2d074254 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1470,6 +1470,7 @@
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
};
jpegdec: jpegdec@18004000 {
@@ -1520,6 +1521,7 @@
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
};
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property
2022-04-21 3:51 [PATCH 0/4] Correct power domain for encoder Allen-KH Cheng
` (2 preceding siblings ...)
2022-04-21 3:51 ` [PATCH 3/4] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes Allen-KH Cheng
@ 2022-04-21 3:51 ` Allen-KH Cheng
2022-04-22 13:47 ` Matthias Brugger
2022-04-25 16:37 ` Rob Herring
2022-04-22 13:49 ` [PATCH 0/4] Correct power domain for encoder Matthias Brugger
4 siblings, 2 replies; 8+ messages in thread
From: Allen-KH Cheng @ 2022-04-21 3:51 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Irui Wang, Allen-KH Cheng
From: Irui Wang <irui.wang@mediatek.com>
Add encoder power domain property
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
index e7b65a91c92c..de2df6c6352c 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
@@ -41,6 +41,9 @@ properties:
assigned-clock-parents: true
+ power-domains:
+ maxItems: 1
+
iommus:
minItems: 1
maxItems: 32
@@ -74,6 +77,7 @@ required:
- iommus
- assigned-clocks
- assigned-clock-parents
+ - power-domains
allOf:
- if:
@@ -135,6 +139,7 @@ examples:
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8173-power.h>
vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
@@ -156,6 +161,7 @@ examples:
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
};
vcodec_enc_vp8: vcodec@19002000 {
@@ -176,4 +182,5 @@ examples:
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
};
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property
2022-04-21 3:51 ` [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property Allen-KH Cheng
@ 2022-04-22 13:47 ` Matthias Brugger
2022-04-25 16:37 ` Rob Herring
1 sibling, 0 replies; 8+ messages in thread
From: Matthias Brugger @ 2022-04-22 13:47 UTC (permalink / raw)
To: Allen-KH Cheng, Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Irui Wang
On 21/04/2022 05:51, Allen-KH Cheng wrote:
> From: Irui Wang <irui.wang@mediatek.com>
>
> Add encoder power domain property
>
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> index e7b65a91c92c..de2df6c6352c 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> @@ -41,6 +41,9 @@ properties:
>
> assigned-clock-parents: true
>
> + power-domains:
> + maxItems: 1
> +
> iommus:
> minItems: 1
> maxItems: 32
> @@ -74,6 +77,7 @@ required:
> - iommus
> - assigned-clocks
> - assigned-clock-parents
> + - power-domains
>
> allOf:
> - if:
> @@ -135,6 +139,7 @@ examples:
> #include <dt-bindings/clock/mt8173-clk.h>
> #include <dt-bindings/memory/mt8173-larb-port.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mt8173-power.h>
>
> vcodec_enc_avc: vcodec@18002000 {
> compatible = "mediatek,mt8173-vcodec-enc";
> @@ -156,6 +161,7 @@ examples:
> clock-names = "venc_sel";
> assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
> };
>
> vcodec_enc_vp8: vcodec@19002000 {
> @@ -176,4 +182,5 @@ examples:
> clock-names = "venc_lt_sel";
> assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
> assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
> };
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property
2022-04-21 3:51 ` [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property Allen-KH Cheng
2022-04-22 13:47 ` Matthias Brugger
@ 2022-04-25 16:37 ` Rob Herring
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring @ 2022-04-25 16:37 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Mauro Carvalho Chehab, Matthias Brugger, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Irui Wang
On Thu, Apr 21, 2022 at 11:51:11AM +0800, Allen-KH Cheng wrote:
> From: Irui Wang <irui.wang@mediatek.com>
>
> Add encoder power domain property
>
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> index e7b65a91c92c..de2df6c6352c 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> @@ -41,6 +41,9 @@ properties:
>
> assigned-clock-parents: true
>
> + power-domains:
> + maxItems: 1
> +
> iommus:
> minItems: 1
> maxItems: 32
> @@ -74,6 +77,7 @@ required:
> - iommus
> - assigned-clocks
> - assigned-clock-parents
> + - power-domains
New properties can't be required as that's an ABI change unless there is
some explanation why it is okay/necessary.
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/4] Correct power domain for encoder
2022-04-21 3:51 [PATCH 0/4] Correct power domain for encoder Allen-KH Cheng
` (3 preceding siblings ...)
2022-04-21 3:51 ` [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property Allen-KH Cheng
@ 2022-04-22 13:49 ` Matthias Brugger
4 siblings, 0 replies; 8+ messages in thread
From: Matthias Brugger @ 2022-04-22 13:49 UTC (permalink / raw)
To: Allen-KH Cheng, Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On 21/04/2022 05:51, Allen-KH Cheng wrote:
> Base on current mediatek encoder driver, we don't use larb driver to
> control power. Add power domain to mediatek,vcodec-encoder.yaml.
> Alos we pick missed PATCHs from 20220117070510.17642-14-yong.wu@mediatek.com
> and add power domain to encoder nodes for mt8173 Soc.
>
> Allen-KH Cheng (1):
> arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
>
> Irui Wang (1):
> dt-bindings: media: mtk-vcodec: Add encoder power domain property
>
> Yong Wu (2):
> arm: dts: mediatek: Get rid of mediatek,larb for MM nodes
> arm64: dts: mediatek: Get rid of mediatek,larb for MM nodes
>
> .../media/mediatek,vcodec-encoder.yaml | 7 +++++++
> arch/arm/boot/dts/mt2701.dtsi | 2 --
> arch/arm/boot/dts/mt7623n.dtsi | 5 -----
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 ++----------------
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------
> 5 files changed, 9 insertions(+), 29 deletions(-)
>
Patch 1 got pushed to v5.18-next/dts32
Patch 2 and 3 got pushed to v5.18-next/dts64
Thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread