From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Tomasz Figa <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>,
Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
<libo.kang@mediatek.com>, <chengci.xu@mediatek.com>
Subject: [PATCH v7 22/36] iommu/mediatek: Add PCIe support
Date: Tue, 3 May 2022 15:14:13 +0800 [thread overview]
Message-ID: <20220503071427.2285-23-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220503071427.2285-1-yong.wu@mediatek.com>
Currently the code for of_iommu_configure_dev_id is like this:
static int of_iommu_configure_dev_id(struct device_node *master_np,
struct device *dev,
const u32 *id)
{
struct of_phandle_args iommu_spec = { .args_count = 1 };
err = of_map_id(master_np, *id, "iommu-map",
"iommu-map-mask", &iommu_spec.np,
iommu_spec.args);
...
}
It supports only one id output. BUT our PCIe HW has two ID(one is for
writing, the other is for reading). I'm not sure if we should change
of_map_id to support output MAX_PHANDLE_ARGS.
Here add the solution in ourselve drivers. If it's pcie case, enable one
more bit.
Not all infra iommu support PCIe, thus add a PCIe support flag here.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ff48506b480c..d63fe28c1403 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -20,6 +20,7 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -134,6 +135,7 @@
#define MTK_IOMMU_TYPE_MASK (0x3 << 13)
/* PM and clock always on. e.g. infra iommu */
#define PM_CLK_AO BIT(15)
+#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -420,8 +422,11 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
peri_mmuen_msk = BIT(portid);
- peri_mmuen = enable ? peri_mmuen_msk : 0;
+ /* PCI dev has only one output id, enable the next writing bit for PCIe */
+ if (dev_is_pci(dev))
+ peri_mmuen_msk |= BIT(portid + 1);
+ peri_mmuen = enable ? peri_mmuen_msk : 0;
ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
peri_mmuen_msk, peri_mmuen);
if (ret)
@@ -1054,6 +1059,15 @@ static int mtk_iommu_probe(struct platform_device *pdev)
ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
if (ret)
goto out_bus_set_null;
+ } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
+ MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
+#ifdef CONFIG_PCI
+ if (!iommu_present(&pci_bus_type)) {
+ ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops);
+ if (ret) /* PCIe fail don't affect platform_bus. */
+ goto out_list_del;
+ }
+#endif
}
return ret;
@@ -1084,6 +1098,11 @@ static int mtk_iommu_remove(struct platform_device *pdev)
if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
device_link_remove(data->smicomm_dev, &pdev->dev);
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
+ } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
+ MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
+#ifdef CONFIG_PCI
+ bus_set_iommu(&pci_bus_type, NULL);
+#endif
}
pm_runtime_disable(&pdev->dev);
devm_free_irq(&pdev->dev, data->irq, data);
--
2.18.0
next prev parent reply other threads:[~2022-05-03 7:18 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 7:13 [PATCH v7 00/36] MT8195 and MT8186 IOMMU SUPPORT Yong Wu
2022-05-03 7:13 ` [PATCH v7 01/36] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2022-05-03 7:13 ` [PATCH v7 02/36] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2022-05-03 7:13 ` [PATCH v7 03/36] dt-bindings: mediatek: mt8186: Add binding for MM iommu Yong Wu
2022-05-03 7:13 ` [PATCH v7 04/36] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2022-05-03 7:13 ` [PATCH v7 05/36] iommu/mediatek: Add list_del in mtk_iommu_remove Yong Wu
2022-05-03 7:13 ` [PATCH v7 06/36] iommu/mediatek: Remove clk_disable " Yong Wu
2022-05-03 7:13 ` [PATCH v7 07/36] iommu/mediatek: Add mutex for m4u_group and m4u_dom in data Yong Wu
2022-05-03 7:13 ` [PATCH v7 08/36] iommu/mediatek: Add mutex for data in the mtk_iommu_domain Yong Wu
2022-05-03 7:14 ` [PATCH v7 09/36] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2022-05-03 7:14 ` [PATCH v7 10/36] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2022-05-03 7:14 ` [PATCH v7 11/36] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2022-05-03 7:14 ` [PATCH v7 12/36] iommu/mediatek: Add a flag STD_AXI_MODE Yong Wu
2022-05-03 7:14 ` [PATCH v7 13/36] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2022-05-03 7:14 ` [PATCH v7 14/36] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2022-05-03 7:14 ` [PATCH v7 15/36] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2022-05-03 7:14 ` [PATCH v7 16/36] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2022-05-03 7:14 ` [PATCH v7 17/36] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2022-05-03 7:14 ` [PATCH v7 18/36] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2022-05-03 7:14 ` [PATCH v7 19/36] iommu/mediatek: Allow IOMMU_DOMAIN_UNMANAGED for PCIe VFIO Yong Wu
2022-05-03 7:14 ` [PATCH v7 20/36] iommu/mediatek: Add a PM_CLK_AO flag for infra iommu Yong Wu
2022-05-03 7:14 ` [PATCH v7 21/36] iommu/mediatek: Add infra iommu support Yong Wu
2022-05-03 7:14 ` Yong Wu [this message]
2022-05-03 7:14 ` [PATCH v7 23/36] iommu/mediatek: Add mt8195 support Yong Wu
2022-05-03 7:14 ` [PATCH v7 24/36] iommu/mediatek: Only adjust code about register base Yong Wu
2022-05-03 7:14 ` [PATCH v7 25/36] iommu/mediatek: Just move code position in hw_init Yong Wu
2022-05-03 7:14 ` [PATCH v7 26/36] iommu/mediatek: Separate mtk_iommu_data for v1 and v2 Yong Wu
2022-05-03 7:14 ` [PATCH v7 27/36] iommu/mediatek: Remove mtk_iommu.h Yong Wu
2022-05-03 7:14 ` [PATCH v7 28/36] iommu/mediatek-v1: Just rename mtk_iommu to mtk_iommu_v1 Yong Wu
2022-05-03 7:14 ` [PATCH v7 29/36] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2022-05-03 7:14 ` [PATCH v7 30/36] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2022-05-03 7:14 ` [PATCH v7 31/36] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2022-05-03 7:14 ` [PATCH v7 32/36] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2022-05-03 7:14 ` [PATCH v7 33/36] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2022-05-03 7:14 ` [PATCH v7 34/36] iommu/mediatek: Backup/restore regsiters for multi banks Yong Wu
2022-05-03 7:14 ` [PATCH v7 35/36] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
2022-05-03 7:14 ` [PATCH v7 36/36] iommu/mediatek: Add mt8186 iommu support Yong Wu
2022-05-03 15:42 ` [PATCH v7 00/36] MT8195 and MT8186 IOMMU SUPPORT Matthias Brugger
2022-05-04 8:40 ` Joerg Roedel
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