From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Tomasz Figa <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>,
Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
<libo.kang@mediatek.com>, <chengci.xu@mediatek.com>
Subject: [PATCH v7 34/36] iommu/mediatek: Backup/restore regsiters for multi banks
Date: Tue, 3 May 2022 15:14:25 +0800 [thread overview]
Message-ID: <20220503071427.2285-35-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220503071427.2285-1-yong.wu@mediatek.com>
Each bank has some independent registers. thus backup/restore them for
each a bank when suspend and resume.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 46 ++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 400dea33aea1..d3e8773b4c47 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -173,11 +173,12 @@ struct mtk_iommu_suspend_reg {
u32 misc_ctrl;
u32 dcm_dis;
u32 ctrl_reg;
- u32 int_control0;
- u32 int_main_control;
- u32 ivrp_paddr;
u32 vld_pa_rng;
u32 wr_len_ctrl;
+
+ u32 int_control[MTK_IOMMU_BANK_MAX];
+ u32 int_main_control[MTK_IOMMU_BANK_MAX];
+ u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
};
struct mtk_iommu_plat_data {
@@ -1302,16 +1303,23 @@ static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
- void __iomem *base = data->bank[0].base;
+ void __iomem *base;
+ int i = 0;
+ base = data->bank[i].base;
reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
- reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
- reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
- reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
+ do {
+ if (!data->plat_data->banks_enable[i])
+ continue;
+ base = data->bank[i].base;
+ reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
+ reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
+ reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
+ } while (++i < data->plat_data->banks_num);
clk_disable_unprepare(data->bclk);
return 0;
}
@@ -1320,9 +1328,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
- struct mtk_iommu_domain *m4u_dom = data->bank[0].m4u_dom;
- void __iomem *base = data->bank[0].base;
- int ret;
+ struct mtk_iommu_domain *m4u_dom;
+ void __iomem *base;
+ int ret, i = 0;
ret = clk_prepare_enable(data->bclk);
if (ret) {
@@ -1334,18 +1342,26 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
* Uppon first resume, only enable the clk and return, since the values of the
* registers are not yet set.
*/
- if (!m4u_dom)
+ if (!reg->wr_len_ctrl)
return 0;
+ base = data->bank[i].base;
writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
- writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
- writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
- writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
+ do {
+ m4u_dom = data->bank[i].m4u_dom;
+ if (!data->plat_data->banks_enable[i] || !m4u_dom)
+ continue;
+ base = data->bank[i].base;
+ writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
+ writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
+ writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
+ base + REG_MMU_PT_BASE_ADDR);
+ } while (++i < data->plat_data->banks_num);
/*
* Users may allocate dma buffer before they call pm_runtime_get,
--
2.18.0
next prev parent reply other threads:[~2022-05-03 7:22 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 7:13 [PATCH v7 00/36] MT8195 and MT8186 IOMMU SUPPORT Yong Wu
2022-05-03 7:13 ` [PATCH v7 01/36] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2022-05-03 7:13 ` [PATCH v7 02/36] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2022-05-03 7:13 ` [PATCH v7 03/36] dt-bindings: mediatek: mt8186: Add binding for MM iommu Yong Wu
2022-05-03 7:13 ` [PATCH v7 04/36] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2022-05-03 7:13 ` [PATCH v7 05/36] iommu/mediatek: Add list_del in mtk_iommu_remove Yong Wu
2022-05-03 7:13 ` [PATCH v7 06/36] iommu/mediatek: Remove clk_disable " Yong Wu
2022-05-03 7:13 ` [PATCH v7 07/36] iommu/mediatek: Add mutex for m4u_group and m4u_dom in data Yong Wu
2022-05-03 7:13 ` [PATCH v7 08/36] iommu/mediatek: Add mutex for data in the mtk_iommu_domain Yong Wu
2022-05-03 7:14 ` [PATCH v7 09/36] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2022-05-03 7:14 ` [PATCH v7 10/36] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2022-05-03 7:14 ` [PATCH v7 11/36] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2022-05-03 7:14 ` [PATCH v7 12/36] iommu/mediatek: Add a flag STD_AXI_MODE Yong Wu
2022-05-03 7:14 ` [PATCH v7 13/36] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2022-05-03 7:14 ` [PATCH v7 14/36] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2022-05-03 7:14 ` [PATCH v7 15/36] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2022-05-03 7:14 ` [PATCH v7 16/36] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2022-05-03 7:14 ` [PATCH v7 17/36] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2022-05-03 7:14 ` [PATCH v7 18/36] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2022-05-03 7:14 ` [PATCH v7 19/36] iommu/mediatek: Allow IOMMU_DOMAIN_UNMANAGED for PCIe VFIO Yong Wu
2022-05-03 7:14 ` [PATCH v7 20/36] iommu/mediatek: Add a PM_CLK_AO flag for infra iommu Yong Wu
2022-05-03 7:14 ` [PATCH v7 21/36] iommu/mediatek: Add infra iommu support Yong Wu
2022-05-03 7:14 ` [PATCH v7 22/36] iommu/mediatek: Add PCIe support Yong Wu
2022-05-03 7:14 ` [PATCH v7 23/36] iommu/mediatek: Add mt8195 support Yong Wu
2022-05-03 7:14 ` [PATCH v7 24/36] iommu/mediatek: Only adjust code about register base Yong Wu
2022-05-03 7:14 ` [PATCH v7 25/36] iommu/mediatek: Just move code position in hw_init Yong Wu
2022-05-03 7:14 ` [PATCH v7 26/36] iommu/mediatek: Separate mtk_iommu_data for v1 and v2 Yong Wu
2022-05-03 7:14 ` [PATCH v7 27/36] iommu/mediatek: Remove mtk_iommu.h Yong Wu
2022-05-03 7:14 ` [PATCH v7 28/36] iommu/mediatek-v1: Just rename mtk_iommu to mtk_iommu_v1 Yong Wu
2022-05-03 7:14 ` [PATCH v7 29/36] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2022-05-03 7:14 ` [PATCH v7 30/36] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2022-05-03 7:14 ` [PATCH v7 31/36] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2022-05-03 7:14 ` [PATCH v7 32/36] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2022-05-03 7:14 ` [PATCH v7 33/36] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2022-05-03 7:14 ` Yong Wu [this message]
2022-05-03 7:14 ` [PATCH v7 35/36] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
2022-05-03 7:14 ` [PATCH v7 36/36] iommu/mediatek: Add mt8186 iommu support Yong Wu
2022-05-03 15:42 ` [PATCH v7 00/36] MT8195 and MT8186 IOMMU SUPPORT Matthias Brugger
2022-05-04 8:40 ` Joerg Roedel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220503071427.2285-35-yong.wu@mediatek.com \
--to=yong.wu@mediatek.com \
--cc=anan.sun@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=chengci.xu@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=hsinyi@chromium.org \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
--cc=krzk@kernel.org \
--cc=libo.kang@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mingyuan.ma@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=tfiga@chromium.org \
--cc=will@kernel.org \
--cc=xueqi.zhang@mediatek.com \
--cc=yen-chang.chen@mediatek.com \
--cc=yf.wang@mediatek.com \
--cc=youlin.pei@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).