[PATCH v2 0/2] MediaTek Helio X10 MT6795 - CQDMA driver

[PATCH v2 0/2] MediaTek Helio X10 MT6795 - CQDMA driver

[AngeloGioacchino Del Regno]

In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.

This series introduces support for CQDMA on the Helio X10 SoC.

Tested on a Sony Xperia M5 (codename "Holly") smartphone.

Changes in v2:
 - Fixed errors around (sorry, at v1 I've sent patches from the wrong folder)

AngeloGioacchino Del Regno (2):
  dmaengine: mediatek-cqdma: Add SoC-specific match data
  dmaengine: mediatek-cqdma: Add support for MediaTek MT6795

 drivers/dma/mediatek/mtk-cqdma.c | 41 ++++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 7 deletions(-)

-- 
2.35.1

[PATCH v2 1/2] dmaengine: mediatek-cqdma: Add SoC-specific match data

[AngeloGioacchino Del Regno]

On some SoCs the DST2 and SRC2 registers may be at a different offset:
add a match data structure and assign it to mt6765 as a preparation
for adding support for more SoCs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/dma/mediatek/mtk-cqdma.c | 35 +++++++++++++++++++++++++-------
 1 file changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index f8847c48ba03..a2fb538d9483 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -48,8 +48,6 @@
 #define MTK_CQDMA_DST			0x20
 #define MTK_CQDMA_LEN1			0x24
 #define MTK_CQDMA_LEN2			0x28
-#define MTK_CQDMA_SRC2			0x60
-#define MTK_CQDMA_DST2			0x64
 
 /* Registers setting */
 #define MTK_CQDMA_EN_BIT		BIT(0)
@@ -126,9 +124,20 @@ struct mtk_cqdma_vchan {
 	bool issue_synchronize;
 };
 
+/**
+ * struct mtk_cqdma_plat_data - SoC specific parameters
+ * @reg_dst2:               dst2 register offset
+ * @reg_src2:               src2 register offset
+ */
+struct mtk_cqdma_plat_data {
+	u8 reg_src2;
+	u8 reg_dst2;
+};
+
 /**
  * struct mtk_cqdma_device - The struct holding info describing CQDMA
  *                          device
+ * @plat:                   SoC-specific platform data
  * @ddev:                   An instance for struct dma_device
  * @clk:                    The clock that device internal is using
  * @dma_requests:           The number of VCs the device supports to
@@ -137,6 +146,7 @@ struct mtk_cqdma_vchan {
  * @pc:                     The pointer to all the underlying PCs
  */
 struct mtk_cqdma_device {
+	const struct mtk_cqdma_plat_data *plat;
 	struct dma_device ddev;
 	struct clk *clk;
 
@@ -231,6 +241,8 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc)
 static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
 			    struct mtk_cqdma_vdesc *cvd)
 {
+	struct mtk_cqdma_device *cqdma = to_cqdma_dev(cvd->ch);
+
 	/* wait for the previous transaction done */
 	if (mtk_cqdma_poll_engine_done(pc, true) < 0)
 		dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait transaction timeout\n");
@@ -243,17 +255,17 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
 	/* setup the source */
 	mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT);
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-	mtk_dma_set(pc, MTK_CQDMA_SRC2, cvd->src >> MTK_CQDMA_ADDR2_SHFIT);
+	mtk_dma_set(pc, cqdma->plat->reg_src2, cvd->src >> MTK_CQDMA_ADDR2_SHFIT);
 #else
-	mtk_dma_set(pc, MTK_CQDMA_SRC2, 0);
+	mtk_dma_set(pc, cqdma->plat->reg_src2, 0);
 #endif
 
 	/* setup the destination */
 	mtk_dma_set(pc, MTK_CQDMA_DST, cvd->dest & MTK_CQDMA_ADDR_LIMIT);
 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-	mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
+	mtk_dma_set(pc, cqdma->plat->reg_dst2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
 #else
-	mtk_dma_set(pc, MTK_CQDMA_DST2, 0);
+	mtk_dma_set(pc, cqdma->plat->reg_dst2, 0);
 #endif
 
 	/* setup the length */
@@ -740,8 +752,13 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
 	pm_runtime_disable(cqdma2dev(cqdma));
 }
 
+static const struct mtk_cqdma_plat_data cqdma_mt6765 = {
+	.reg_dst2 = 0x64,
+	.reg_src2 = 0x60,
+};
+
 static const struct of_device_id mtk_cqdma_match[] = {
-	{ .compatible = "mediatek,mt6765-cqdma" },
+	{ .compatible = "mediatek,mt6765-cqdma", .data = &cqdma_mt6765 },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
@@ -758,6 +775,10 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
 	if (!cqdma)
 		return -ENOMEM;
 
+	cqdma->plat = device_get_match_data(&pdev->dev);
+	if (cqdma->plat)
+		return -EINVAL;
+
 	dd = &cqdma->ddev;
 
 	cqdma->clk = devm_clk_get(&pdev->dev, "cqdma");
-- 
2.35.1

[PATCH v2 2/2] dmaengine: mediatek-cqdma: Add support for MediaTek MT6795

[AngeloGioacchino Del Regno]

Add a compatible string and platform data for the Helio X10 MT6795 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/dma/mediatek/mtk-cqdma.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index a2fb538d9483..e1772dbf50d5 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -757,8 +757,14 @@ static const struct mtk_cqdma_plat_data cqdma_mt6765 = {
 	.reg_src2 = 0x60,
 };
 
+static const struct mtk_cqdma_plat_data cqdma_mt6795 = {
+	.reg_dst2 = 0x44,
+	.reg_src2 = 0x40,
+};
+
 static const struct of_device_id mtk_cqdma_match[] = {
 	{ .compatible = "mediatek,mt6765-cqdma", .data = &cqdma_mt6765 },
+	{ .compatible = "mediatek,mt6795-cqdma", .data = &cqdma_mt6795 },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
-- 
2.35.1

Re: [PATCH v2 1/2] dmaengine: mediatek-cqdma: Add SoC-specific match data

[Vinod Koul]

On 03-05-22, 16:06, AngeloGioacchino Del Regno wrote:
> On some SoCs the DST2 and SRC2 registers may be at a different offset:
> add a match data structure and assign it to mt6765 as a preparation
> for adding support for more SoCs.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/dma/mediatek/mtk-cqdma.c | 35 +++++++++++++++++++++++++-------
>  1 file changed, 28 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index f8847c48ba03..a2fb538d9483 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -48,8 +48,6 @@
>  #define MTK_CQDMA_DST			0x20
>  #define MTK_CQDMA_LEN1			0x24
>  #define MTK_CQDMA_LEN2			0x28
> -#define MTK_CQDMA_SRC2			0x60
> -#define MTK_CQDMA_DST2			0x64
>  
>  /* Registers setting */
>  #define MTK_CQDMA_EN_BIT		BIT(0)
> @@ -126,9 +124,20 @@ struct mtk_cqdma_vchan {
>  	bool issue_synchronize;
>  };
>  
> +/**
> + * struct mtk_cqdma_plat_data - SoC specific parameters
> + * @reg_dst2:               dst2 register offset
> + * @reg_src2:               src2 register offset
> + */
> +struct mtk_cqdma_plat_data {
> +	u8 reg_src2;
> +	u8 reg_dst2;
> +};
> +
>  /**
>   * struct mtk_cqdma_device - The struct holding info describing CQDMA
>   *                          device
> + * @plat:                   SoC-specific platform data
>   * @ddev:                   An instance for struct dma_device
>   * @clk:                    The clock that device internal is using
>   * @dma_requests:           The number of VCs the device supports to
> @@ -137,6 +146,7 @@ struct mtk_cqdma_vchan {
>   * @pc:                     The pointer to all the underlying PCs
>   */
>  struct mtk_cqdma_device {
> +	const struct mtk_cqdma_plat_data *plat;
>  	struct dma_device ddev;
>  	struct clk *clk;
>  
> @@ -231,6 +241,8 @@ static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc)
>  static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
>  			    struct mtk_cqdma_vdesc *cvd)
>  {
> +	struct mtk_cqdma_device *cqdma = to_cqdma_dev(cvd->ch);
> +
>  	/* wait for the previous transaction done */
>  	if (mtk_cqdma_poll_engine_done(pc, true) < 0)
>  		dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait transaction timeout\n");
> @@ -243,17 +255,17 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
>  	/* setup the source */
>  	mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT);
>  #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> -	mtk_dma_set(pc, MTK_CQDMA_SRC2, cvd->src >> MTK_CQDMA_ADDR2_SHFIT);
> +	mtk_dma_set(pc, cqdma->plat->reg_src2, cvd->src >> MTK_CQDMA_ADDR2_SHFIT);
>  #else
> -	mtk_dma_set(pc, MTK_CQDMA_SRC2, 0);
> +	mtk_dma_set(pc, cqdma->plat->reg_src2, 0);
>  #endif
>  
>  	/* setup the destination */
>  	mtk_dma_set(pc, MTK_CQDMA_DST, cvd->dest & MTK_CQDMA_ADDR_LIMIT);
>  #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> -	mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
> +	mtk_dma_set(pc, cqdma->plat->reg_dst2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
>  #else
> -	mtk_dma_set(pc, MTK_CQDMA_DST2, 0);
> +	mtk_dma_set(pc, cqdma->plat->reg_dst2, 0);
>  #endif
>  
>  	/* setup the length */
> @@ -740,8 +752,13 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
>  	pm_runtime_disable(cqdma2dev(cqdma));
>  }
>  
> +static const struct mtk_cqdma_plat_data cqdma_mt6765 = {
> +	.reg_dst2 = 0x64,
> +	.reg_src2 = 0x60,

Please use the macros instead of magic numbers here

> +};
> +
>  static const struct of_device_id mtk_cqdma_match[] = {
> -	{ .compatible = "mediatek,mt6765-cqdma" },
> +	{ .compatible = "mediatek,mt6765-cqdma", .data = &cqdma_mt6765 },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
> @@ -758,6 +775,10 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
>  	if (!cqdma)
>  		return -ENOMEM;
>  
> +	cqdma->plat = device_get_match_data(&pdev->dev);
> +	if (cqdma->plat)
> +		return -EINVAL;
> +
>  	dd = &cqdma->ddev;
>  
>  	cqdma->clk = devm_clk_get(&pdev->dev, "cqdma");
> -- 
> 2.35.1

-- 
~Vinod

Re: [PATCH v2 2/2] dmaengine: mediatek-cqdma: Add support for MediaTek MT6795

[Vinod Koul]

On 03-05-22, 16:06, AngeloGioacchino Del Regno wrote:
> Add a compatible string and platform data for the Helio X10 MT6795 SoC.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/dma/mediatek/mtk-cqdma.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index a2fb538d9483..e1772dbf50d5 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -757,8 +757,14 @@ static const struct mtk_cqdma_plat_data cqdma_mt6765 = {
>  	.reg_src2 = 0x60,
>  };
>  
> +static const struct mtk_cqdma_plat_data cqdma_mt6795 = {
> +	.reg_dst2 = 0x44,
> +	.reg_src2 = 0x40,

Please define these registers

> +};
> +
>  static const struct of_device_id mtk_cqdma_match[] = {
>  	{ .compatible = "mediatek,mt6765-cqdma", .data = &cqdma_mt6765 },
> +	{ .compatible = "mediatek,mt6795-cqdma", .data = &cqdma_mt6795 },

where is this documented?

>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
> -- 
> 2.35.1

-- 
~Vinod