* [PATCH v3 0/6] SM8350 Display/GPU clock enablement
@ 2022-05-04 12:27 Robert Foss
2022-05-04 12:27 ` [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss
This series depends on a patch[1] for parked RCGs, which is being reviewed seperately from this series.
Additionally this series is pending a decision about .fw_name .index for new drivers, so please don't merge this yet.
[1] https://lore.kernel.org/linux-arm-msm/20220426212136.1543984-1-bjorn.andersson@linaro.org/
Changes since v2
- Dropped "clk: Introduce CLK_ASSUME_ENABLED_WHEN_UNUSED"
- Dropped "clk: qcom: sm8250-dispcc: Flag shared RCGs as assumed enable"
- Dropped "clk: qcom: rcg2: Cache rate changes for parked RCGs"
Jonathan Marek (3):
clk: qcom: add support for SM8350 GPUCC
clk: qcom: add support for SM8350 DISPCC
dt-bindings: clock: Add Qcom SM8350 DISPCC bindings
Robert Foss (3):
arm64: dts: qcom: sm8350: Replace integers with rpmpd defines
dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
arm64: dts: qcom: sm8350: Add DISPCC node
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +-
.../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8350.dtsi | 42 +-
drivers/clk/qcom/Kconfig | 12 +-
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/dispcc-sm8250.c | 60 +-
drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 +
include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++
9 files changed, 800 insertions(+), 13 deletions(-)
create mode 100644 drivers/clk/qcom/gpucc-sm8350.c
create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
2022-05-04 12:27 ` [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss
Replace &rpmhpd power domain integers with their respective defines
in order to improve legibility.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c0137bdcf94b..52428b6df64e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 0>,
- <&rpmhpd 12>;
+ power-domains = <&rpmhpd SM8350_CX>,
+ <&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
@@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 4>,
- <&rpmhpd 5>;
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
@@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 0>,
- <&rpmhpd 10>;
+ power-domains = <&rpmhpd SM8350_CX>,
+ <&rpmhpd SM8350_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
@@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 4>,
- <&rpmhpd 5>;
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
2022-05-04 12:27 ` [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
2022-05-04 13:34 ` Dmitry Baryshkov
2022-05-04 12:27 ` [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss
From: Jonathan Marek <jonathan@marek.ca>
The GPUCC manages the clocks for the Adreno GPU found on the
sm8350 SoCs.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
Changes since v1
- Remove .name assignments for clk_parent_data - Dmitry
- Use ARRAY_SIZE where possible - Dmitry
- Remove commented out code - Dmitry
- Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry
- Assign .parent_hws instead of .hw - Dmitry
Changes since v2
- Switch license to dual BSD/GPL - Bjorn
- Add Jonathans SoB - Jonathan
- Add Linaro to copyright statement - Bjorn
- Make .hw.init assignment const - Bjorn
- Extract & deduplicate bi_tcxo parent_data - Bjorn
- Removed further .name assignment - Bjorn
- Move of_device_id declaration - Bjorn
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++
3 files changed, 646 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-sm8350.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e27f37ac2d9c..9b1f54e634b9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -703,6 +703,14 @@ config SM_GPUCC_8250
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
+config SM_GPUCC_8350
+ tristate "SM8350 Graphics Clock Controller"
+ select SM_GCC_8350
+ help
+ Support for the graphics clock controller on SM8350 devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config SM_VIDEOCC_8150
tristate "SM8150 Video Clock Controller"
select SM_GCC_8150
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index dff6aeb980e6..e1b7e49c8da4 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
+obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
new file mode 100644
index 000000000000..68d85757e064
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sm8350.c
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-divider.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL0_OUT_MAIN_DIV,
+ P_GPU_CC_PLL0_OUT_MAIN,
+ P_GPU_CC_PLL1_OUT_MAIN,
+};
+
+static struct pll_vco lucid_5lpe_vco[] = {
+ { 249600000, 1750000000, 0 },
+};
+
+static const struct alpha_pll_config gpu_cc_pll0_config = {
+ .l = 0x18,
+ .alpha = 0x6000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x2A9A699C,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000000,
+ .test_ctl_hi1_val = 0x01800000,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static const struct clk_parent_data gpu_cc_parent = {
+ .fw_name = "bi_tcxo",
+};
+
+static struct clk_alpha_pll gpu_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_5lpe_vco,
+ .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_pll0",
+ .parent_data = &gpu_cc_parent,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_5lpe_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config gpu_cc_pll1_config = {
+ .l = 0x1A,
+ .alpha = 0xAAA,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x2A9A699C,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000000,
+ .test_ctl_hi1_val = 0x01800000,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+ .offset = 0x100,
+ .vco_table = lucid_5lpe_vco,
+ .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_pll1",
+ .parent_data = &gpu_cc_parent,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_5lpe_ops,
+ },
+ },
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL0_OUT_MAIN, 1 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_0[] = {
+ gpu_cc_parent,
+ { .hw = &gpu_cc_pll0.clkr.hw },
+ { .hw = &gpu_cc_pll1.clkr.hw },
+ { .fw_name = "gcc_gpu_gpll0_clk_src" },
+ { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
+};
+
+static const struct parent_map gpu_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_1[] = {
+ gpu_cc_parent,
+ { .hw = &gpu_cc_pll1.clkr.hw },
+ { .fw_name = "gcc_gpu_gpll0_clk_src" },
+ { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
+ F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+ .cmd_rcgr = 0x1120,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_0,
+ .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_gmu_clk_src",
+ .parent_data = gpu_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
+ F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_hub_clk_src = {
+ .cmd_rcgr = 0x117c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_1,
+ .freq_tbl = ftbl_gpu_cc_hub_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_hub_clk_src",
+ .parent_data = gpu_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
+ .reg = 0x11c0,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpu_cc_hub_ahb_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
+ .reg = 0x11bc,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpu_cc_hub_cx_int_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gpu_cc_ahb_clk = {
+ .halt_reg = 0x1078,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1078,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cb_clk = {
+ .halt_reg = 0x1170,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1170,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+ .halt_reg = 0x107c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x107c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_crc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_apb_clk = {
+ .halt_reg = 0x1088,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1088,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_apb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+ .halt_reg = 0x1098,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1098,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_gmu_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_gmu_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_qdss_at_clk = {
+ .halt_reg = 0x1080,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_qdss_at_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
+ .halt_reg = 0x1094,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_qdss_trig_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
+ .halt_reg = 0x1084,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_qdss_tsctr_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+ .halt_reg = 0x108c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x108c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cx_snoc_dvm_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+ .halt_reg = 0x1004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cxo_aon_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+ .halt_reg = 0x109c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x109c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_cxo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_freq_measure_clk = {
+ .halt_reg = 0x120c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x120c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_freq_measure_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_gx_gmu_clk = {
+ .halt_reg = 0x1064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1064,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_gx_gmu_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_gmu_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
+ .halt_reg = 0x105c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x105c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_gx_qdss_tsctr_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_gx_vsense_clk = {
+ .halt_reg = 0x1058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_gx_vsense_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
+ .halt_reg = 0x5000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hub_aon_clk = {
+ .halt_reg = 0x1178,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1178,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_hub_aon_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hub_cx_int_clk = {
+ .halt_reg = 0x1204,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1204,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_hub_cx_int_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
+ .halt_reg = 0x802c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x802c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_mnd1x_0_gfx3d_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
+ .halt_reg = 0x8030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_mnd1x_1_gfx3d_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_sleep_clk = {
+ .halt_reg = 0x1090,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1090,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpu_cc_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc gpu_cx_gdsc = {
+ .gdscr = 0x106c,
+ .gds_hw_ctrl = 0x1540,
+ .pd = {
+ .name = "gpu_cx_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc gpu_gx_gdsc = {
+ .gdscr = 0x100c,
+ .clamp_io_ctrl = 0x1508,
+ .pd = {
+ .name = "gpu_gx_gdsc",
+ .power_on = gdsc_gx_do_nothing_enable,
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
+};
+
+static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
+ [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
+ [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
+ [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+ [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
+ [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+ [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
+ [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
+ [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
+ [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+ [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+ [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+ [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
+ [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+ [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
+ [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
+ [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
+ [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
+ [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
+ [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
+ [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
+ [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
+ [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
+ [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
+ [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
+ [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
+ [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+ [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
+};
+
+static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
+ [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
+ [GPUCC_GPU_CC_CB_BCR] = { 0x116c },
+ [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
+ [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
+ [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
+ [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
+ [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
+ [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
+};
+
+static struct gdsc *gpu_cc_sm8350_gdscs[] = {
+ [GPU_CX_GDSC] = &gpu_cx_gdsc,
+ [GPU_GX_GDSC] = &gpu_gx_gdsc,
+};
+
+static const struct regmap_config gpu_cc_sm8350_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x8030,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
+ .config = &gpu_cc_sm8350_regmap_config,
+ .clks = gpu_cc_sm8350_clocks,
+ .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
+ .resets = gpu_cc_sm8350_resets,
+ .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
+ .gdscs = gpu_cc_sm8350_gdscs,
+ .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
+};
+
+static int gpu_cc_sm8350_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
+ if (IS_ERR(regmap)) {
+ dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
+ return PTR_ERR(regmap);
+ }
+
+ clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
+ clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
+
+ return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
+}
+
+static const struct of_device_id gpu_cc_sm8350_match_table[] = {
+ { .compatible = "qcom,sm8350-gpucc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
+
+static struct platform_driver gpu_cc_sm8350_driver = {
+ .probe = gpu_cc_sm8350_probe,
+ .driver = {
+ .name = "sm8350-gpucc",
+ .of_match_table = gpu_cc_sm8350_match_table,
+ },
+};
+
+static int __init gpu_cc_sm8350_init(void)
+{
+ return platform_driver_register(&gpu_cc_sm8350_driver);
+}
+subsys_initcall(gpu_cc_sm8350_init);
+
+static void __exit gpu_cc_sm8350_exit(void)
+{
+ platform_driver_unregister(&gpu_cc_sm8350_driver);
+}
+module_exit(gpu_cc_sm8350_exit);
+
+MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
2022-05-04 12:27 ` [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss
2022-05-04 12:27 ` [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
2022-05-16 23:50 ` Rob Herring
2022-05-04 12:27 ` [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss, Dmitry Baryshkov
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8350 SoCs.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++
2 files changed, 54 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 9ebcb1943b0a..4090cc7ea2ae 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -20,6 +20,7 @@ description: |
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
+ dt-bindings/clock/qcom,gpucc-sm8350.h
properties:
compatible:
@@ -31,6 +32,7 @@ properties:
- qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc
+ - qcom,sm8350-gpucc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
new file mode 100644
index 000000000000..d2294e0d527e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CRC_AHB_CLK 2
+#define GPU_CC_CX_APB_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CX_QDSS_AT_CLK 5
+#define GPU_CC_CX_QDSS_TRIG_CLK 6
+#define GPU_CC_CX_QDSS_TSCTR_CLK 7
+#define GPU_CC_CX_SNOC_DVM_CLK 8
+#define GPU_CC_CXO_AON_CLK 9
+#define GPU_CC_CXO_CLK 10
+#define GPU_CC_FREQ_MEASURE_CLK 11
+#define GPU_CC_GMU_CLK_SRC 12
+#define GPU_CC_GX_GMU_CLK 13
+#define GPU_CC_GX_QDSS_TSCTR_CLK 14
+#define GPU_CC_GX_VSENSE_CLK 15
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
+#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
+#define GPU_CC_HUB_AON_CLK 18
+#define GPU_CC_HUB_CLK_SRC 19
+#define GPU_CC_HUB_CX_INT_CLK 20
+#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
+#define GPU_CC_MND1X_0_GFX3D_CLK 22
+#define GPU_CC_MND1X_1_GFX3D_CLK 23
+#define GPU_CC_PLL0 24
+#define GPU_CC_PLL1 25
+#define GPU_CC_SLEEP_CLK 26
+
+/* GPU_CC resets */
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CB_BCR 1
+#define GPUCC_GPU_CC_CX_BCR 2
+#define GPUCC_GPU_CC_FAST_HUB_BCR 3
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
+#define GPUCC_GPU_CC_GMU_BCR 5
+#define GPUCC_GPU_CC_GX_BCR 6
+#define GPUCC_GPU_CC_XO_BCR 7
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
` (2 preceding siblings ...)
2022-05-04 12:27 ` [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
2022-05-04 16:23 ` Konrad Dybcio
2022-05-04 12:27 ` [PATCH v3 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss
2022-05-04 12:27 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss
5 siblings, 1 reply; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss
From: Jonathan Marek <jonathan@marek.ca>
Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes since v1
- Remove comment - Dmitry
Changes since v2
- Add my SoB - Bjorn
- Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag
drivers/clk/qcom/Kconfig | 4 +--
drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++-
2 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9b1f54e634b9..1752ca0ee405 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -609,11 +609,11 @@ config SM_DISPCC_6125
splash screen
config SM_DISPCC_8250
- tristate "SM8150 and SM8250 Display Clock Controller"
+ tristate "SM8150/SM8250/SM8350 Display Clock Controller"
depends on SM_GCC_8150 || SM_GCC_8250
help
Support for the display clock controller on Qualcomm Technologies, Inc
- SM8150 and SM8250 devices.
+ SM8150/SM8250/SM8350 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index db9379634fb2..8e6cb990e387 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = {
{ 249600000, 2000000000, 0 },
};
+static struct pll_vco lucid_5lpe_vco[] = {
+ { 249600000, 1750000000, 0 },
+};
+
static struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x47,
.alpha = 0xE000,
@@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sc8180x-dispcc" },
{ .compatible = "qcom,sm8150-dispcc" },
{ .compatible = "qcom,sm8250-dispcc" },
+ { .compatible = "qcom,sm8350-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
@@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
- /* note: trion == lucid, except for the prepare() op */
+ /* Apply differences for SM8150 and SM8350 */
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
@@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
+ } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
+ static struct clk_rcg2 * const rcgs[] = {
+ &disp_cc_mdss_byte0_clk_src,
+ &disp_cc_mdss_byte1_clk_src,
+ &disp_cc_mdss_dp_aux1_clk_src,
+ &disp_cc_mdss_dp_aux_clk_src,
+ &disp_cc_mdss_dp_link1_clk_src,
+ &disp_cc_mdss_dp_link_clk_src,
+ &disp_cc_mdss_dp_pixel1_clk_src,
+ &disp_cc_mdss_dp_pixel2_clk_src,
+ &disp_cc_mdss_dp_pixel_clk_src,
+ &disp_cc_mdss_esc0_clk_src,
+ &disp_cc_mdss_mdp_clk_src,
+ &disp_cc_mdss_pclk0_clk_src,
+ &disp_cc_mdss_pclk1_clk_src,
+ &disp_cc_mdss_rot_clk_src,
+ &disp_cc_mdss_vsync_clk_src,
+ };
+ static struct clk_regmap_div * const divs[] = {
+ &disp_cc_mdss_byte0_div_clk_src,
+ &disp_cc_mdss_byte1_div_clk_src,
+ &disp_cc_mdss_dp_link1_div_clk_src,
+ &disp_cc_mdss_dp_link_div_clk_src,
+ };
+ unsigned int i;
+ static bool offset_applied;
+
+ /* only apply the offsets once (in case of deferred probe) */
+ if (!offset_applied) {
+ for (i = 0; i < ARRAY_SIZE(rcgs); i++)
+ rcgs[i]->cmd_rcgr -= 4;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ divs[i]->reg -= 4;
+ divs[i]->width = 4;
+ }
+
+ disp_cc_mdss_ahb_clk.halt_reg -= 4;
+ disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
+
+ offset_applied = true;
+ }
+
+ disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
+
+ disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
+ disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
+ disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
+ disp_cc_pll0.vco_table = lucid_5lpe_vco;
+ disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
+ disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
+ disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
+ disp_cc_pll1.vco_table = lucid_5lpe_vco;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
` (3 preceding siblings ...)
2022-05-04 12:27 ` [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
2022-05-04 12:27 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss
5 siblings, 0 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss, Rob Herring
From: Jonathan Marek <jonathan@marek.ca>
Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250
bindings. Update the documentation with the new compatible.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes since v2
- Add my SoB - Bjorn
.../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++--
include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 31497677e8de..7a8d375e055e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -4,18 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SM8150 and SM8250.
+ power domains on SM8150/SM8250/SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
+ dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:
@@ -23,6 +24,7 @@ properties:
- qcom,sc8180x-dispcc
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc
+ - qcom,sm8350-dispcc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
new file mode 120000
index 000000000000..0312b4544acb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 6/6] arm64: dts: qcom: sm8350: Add DISPCC node
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
` (4 preceding siblings ...)
2022-05-04 12:27 ` [PATCH v3 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss
@ 2022-05-04 12:27 ` Robert Foss
5 siblings, 0 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-04 12:27 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
Cc: Robert Foss
Add the dispcc clock-controller DT node for sm8350.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes since v2
- Remove interconnect include - Bjorn
arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 52428b6df64e..99464cd1299e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -2525,6 +2526,31 @@ usb_2_dwc3: usb@a800000 {
};
};
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8350-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domain-names = "mmcx";
+ };
+
adsp: remoteproc@17300000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC
2022-05-04 12:27 ` [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss
@ 2022-05-04 13:34 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2022-05-04 13:34 UTC (permalink / raw)
To: Robert Foss
Cc: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On Wed, 4 May 2022 at 15:27, Robert Foss <robert.foss@linaro.org> wrote:
>
> From: Jonathan Marek <jonathan@marek.ca>
>
> The GPUCC manages the clocks for the Adreno GPU found on the
> sm8350 SoCs.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
These should come in opposite order.
First comes Jonathan's signature. Then you sign under his signature.
> ---
>
> Changes since v1
> - Remove .name assignments for clk_parent_data - Dmitry
> - Use ARRAY_SIZE where possible - Dmitry
> - Remove commented out code - Dmitry
> - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry
> - Assign .parent_hws instead of .hw - Dmitry
>
> Changes since v2
> - Switch license to dual BSD/GPL - Bjorn
> - Add Jonathans SoB - Jonathan
> - Add Linaro to copyright statement - Bjorn
> - Make .hw.init assignment const - Bjorn
> - Extract & deduplicate bi_tcxo parent_data - Bjorn
> - Removed further .name assignment - Bjorn
> - Move of_device_id declaration - Bjorn
>
>
> drivers/clk/qcom/Kconfig | 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++
> 3 files changed, 646 insertions(+)
> create mode 100644 drivers/clk/qcom/gpucc-sm8350.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e27f37ac2d9c..9b1f54e634b9 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -703,6 +703,14 @@ config SM_GPUCC_8250
> Say Y if you want to support graphics controller devices and
> functionality such as 3D graphics.
>
> +config SM_GPUCC_8350
> + tristate "SM8350 Graphics Clock Controller"
> + select SM_GCC_8350
> + help
> + Support for the graphics clock controller on SM8350 devices.
> + Say Y if you want to support graphics controller devices and
> + functionality such as 3D graphics.
> +
> config SM_VIDEOCC_8150
> tristate "SM8150 Video Clock Controller"
> select SM_GCC_8150
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index dff6aeb980e6..e1b7e49c8da4 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -100,6 +100,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
> obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
> obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
> obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
> +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
> obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
> obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
> diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
> new file mode 100644
> index 000000000000..68d85757e064
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-sm8350.c
> @@ -0,0 +1,637 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
> +/*
> + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-divider.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_GPLL0_OUT_MAIN,
> + P_GPLL0_OUT_MAIN_DIV,
> + P_GPU_CC_PLL0_OUT_MAIN,
> + P_GPU_CC_PLL1_OUT_MAIN,
> +};
> +
> +static struct pll_vco lucid_5lpe_vco[] = {
> + { 249600000, 1750000000, 0 },
> +};
> +
> +static const struct alpha_pll_config gpu_cc_pll0_config = {
> + .l = 0x18,
> + .alpha = 0x6000,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00002261,
> + .config_ctl_hi1_val = 0x2A9A699C,
> + .test_ctl_val = 0x00000000,
> + .test_ctl_hi_val = 0x00000000,
> + .test_ctl_hi1_val = 0x01800000,
> + .user_ctl_val = 0x00000000,
> + .user_ctl_hi_val = 0x00000805,
> + .user_ctl_hi1_val = 0x00000000,
> +};
> +
> +static const struct clk_parent_data gpu_cc_parent = {
> + .fw_name = "bi_tcxo",
> +};
> +
> +static struct clk_alpha_pll gpu_cc_pll0 = {
> + .offset = 0x0,
> + .vco_table = lucid_5lpe_vco,
> + .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr = {
> + .hw.init = &(const struct clk_init_data){
> + .name = "gpu_cc_pll0",
> + .parent_data = &gpu_cc_parent,
> + .num_parents = 1,
If you move the parent data away, please use ARRAY_SIZE here (and below).
> + .ops = &clk_alpha_pll_lucid_5lpe_ops,
> + },
> + },
> +};
> +
> +static const struct alpha_pll_config gpu_cc_pll1_config = {
> + .l = 0x1A,
> + .alpha = 0xAAA,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00002261,
> + .config_ctl_hi1_val = 0x2A9A699C,
> + .test_ctl_val = 0x00000000,
> + .test_ctl_hi_val = 0x00000000,
> + .test_ctl_hi1_val = 0x01800000,
> + .user_ctl_val = 0x00000000,
> + .user_ctl_hi_val = 0x00000805,
> + .user_ctl_hi1_val = 0x00000000,
> +};
> +
> +static struct clk_alpha_pll gpu_cc_pll1 = {
> + .offset = 0x100,
> + .vco_table = lucid_5lpe_vco,
> + .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_pll1",
> + .parent_data = &gpu_cc_parent,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_lucid_5lpe_ops,
> + },
> + },
> +};
> +
> +static const struct parent_map gpu_cc_parent_map_0[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPU_CC_PLL0_OUT_MAIN, 1 },
> + { P_GPU_CC_PLL1_OUT_MAIN, 3 },
> + { P_GPLL0_OUT_MAIN, 5 },
> + { P_GPLL0_OUT_MAIN_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gpu_cc_parent_data_0[] = {
> + gpu_cc_parent,
> + { .hw = &gpu_cc_pll0.clkr.hw },
> + { .hw = &gpu_cc_pll1.clkr.hw },
> + { .fw_name = "gcc_gpu_gpll0_clk_src" },
> + { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
> +};
> +
> +static const struct parent_map gpu_cc_parent_map_1[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPU_CC_PLL1_OUT_MAIN, 3 },
> + { P_GPLL0_OUT_MAIN, 5 },
> + { P_GPLL0_OUT_MAIN_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gpu_cc_parent_data_1[] = {
> + gpu_cc_parent,
> + { .hw = &gpu_cc_pll1.clkr.hw },
> + { .fw_name = "gcc_gpu_gpll0_clk_src" },
> + { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
> +};
> +
> +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
> + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gpu_cc_gmu_clk_src = {
> + .cmd_rcgr = 0x1120,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gpu_cc_parent_map_0,
> + .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_gmu_clk_src",
> + .parent_data = gpu_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
> + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
> + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gpu_cc_hub_clk_src = {
> + .cmd_rcgr = 0x117c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gpu_cc_parent_map_1,
> + .freq_tbl = ftbl_gpu_cc_hub_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_hub_clk_src",
> + .parent_data = gpu_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
> + .reg = 0x11c0,
> + .shift = 0,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gpu_cc_hub_ahb_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
> + .reg = 0x11bc,
> + .shift = 0,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gpu_cc_hub_cx_int_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_branch gpu_cc_ahb_clk = {
> + .halt_reg = 0x1078,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1078,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cb_clk = {
> + .halt_reg = 0x1170,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1170,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_crc_ahb_clk = {
> + .halt_reg = 0x107c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x107c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_crc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_apb_clk = {
> + .halt_reg = 0x1088,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1088,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_apb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_gmu_clk = {
> + .halt_reg = 0x1098,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1098,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_gmu_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_gmu_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_aon_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_qdss_at_clk = {
> + .halt_reg = 0x1080,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1080,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_qdss_at_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
> + .halt_reg = 0x1094,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1094,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_qdss_trig_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
> + .halt_reg = 0x1084,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1084,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_qdss_tsctr_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
> + .halt_reg = 0x108c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x108c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_snoc_dvm_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cxo_aon_clk = {
> + .halt_reg = 0x1004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cxo_aon_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cxo_clk = {
> + .halt_reg = 0x109c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x109c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cxo_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_freq_measure_clk = {
> + .halt_reg = 0x120c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x120c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_freq_measure_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_gx_gmu_clk = {
> + .halt_reg = 0x1064,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1064,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_gx_gmu_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_gmu_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
> + .halt_reg = 0x105c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x105c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_gx_qdss_tsctr_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_gx_vsense_clk = {
> + .halt_reg = 0x1058,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_gx_vsense_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
> + .halt_reg = 0x5000,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x5000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_hub_aon_clk = {
> + .halt_reg = 0x1178,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1178,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_hub_aon_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_aon_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_hub_cx_int_clk = {
> + .halt_reg = 0x1204,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1204,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_hub_cx_int_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_aon_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
> + .halt_reg = 0x802c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x802c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_mnd1x_0_gfx3d_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
> + .halt_reg = 0x8030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x8030,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_mnd1x_1_gfx3d_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_sleep_clk = {
> + .halt_reg = 0x1090,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x1090,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct gdsc gpu_cx_gdsc = {
> + .gdscr = 0x106c,
> + .gds_hw_ctrl = 0x1540,
> + .pd = {
> + .name = "gpu_cx_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +static struct gdsc gpu_gx_gdsc = {
> + .gdscr = 0x100c,
> + .clamp_io_ctrl = 0x1508,
> + .pd = {
> + .name = "gpu_gx_gdsc",
> + .power_on = gdsc_gx_do_nothing_enable,
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
> +};
> +
> +static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
> + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
> + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
> + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
> + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
> + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
> + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
> + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
> + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
> + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
> + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
> + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
> + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
> + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
> + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
> + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
> + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
> + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
> + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
> + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
> + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
> + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
> + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
> + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
> + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
> + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
> + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
> + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
> +};
> +
> +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
> + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
> + [GPUCC_GPU_CC_CB_BCR] = { 0x116c },
> + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
> + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
> + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
> + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
> + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
> + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
> +};
> +
> +static struct gdsc *gpu_cc_sm8350_gdscs[] = {
> + [GPU_CX_GDSC] = &gpu_cx_gdsc,
> + [GPU_GX_GDSC] = &gpu_gx_gdsc,
> +};
> +
> +static const struct regmap_config gpu_cc_sm8350_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x8030,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
> + .config = &gpu_cc_sm8350_regmap_config,
> + .clks = gpu_cc_sm8350_clocks,
> + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
> + .resets = gpu_cc_sm8350_resets,
> + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
> + .gdscs = gpu_cc_sm8350_gdscs,
> + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
> +};
> +
> +static int gpu_cc_sm8350_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
> + if (IS_ERR(regmap)) {
> + dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
> + return PTR_ERR(regmap);
> + }
> +
> + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
> + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
> +
> + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
> +}
> +
> +static const struct of_device_id gpu_cc_sm8350_match_table[] = {
> + { .compatible = "qcom,sm8350-gpucc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
> +
> +static struct platform_driver gpu_cc_sm8350_driver = {
> + .probe = gpu_cc_sm8350_probe,
> + .driver = {
> + .name = "sm8350-gpucc",
> + .of_match_table = gpu_cc_sm8350_match_table,
> + },
> +};
> +
> +static int __init gpu_cc_sm8350_init(void)
> +{
> + return platform_driver_register(&gpu_cc_sm8350_driver);
> +}
> +subsys_initcall(gpu_cc_sm8350_init);
> +
> +static void __exit gpu_cc_sm8350_exit(void)
> +{
> + platform_driver_unregister(&gpu_cc_sm8350_driver);
> +}
> +module_exit(gpu_cc_sm8350_exit);
> +
> +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC
2022-05-04 12:27 ` [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss
@ 2022-05-04 16:23 ` Konrad Dybcio
2022-05-12 13:21 ` Robert Foss
0 siblings, 1 reply; 12+ messages in thread
From: Konrad Dybcio @ 2022-05-04 16:23 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, mturquette, sboyd, robh+dt,
krzk+dt, jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
On 04/05/2022 14:27, Robert Foss wrote:
> From: Jonathan Marek <jonathan@marek.ca>
>
> Add support to the SM8350 display clock controller by extending the SM8250
> display clock controller, which is almost identical but has some minor
> differences.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>
> Changes since v1
> - Remove comment - Dmitry
>
> Changes since v2
> - Add my SoB - Bjorn
> - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag
>
>
> drivers/clk/qcom/Kconfig | 4 +--
> drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++-
> 2 files changed, 61 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9b1f54e634b9..1752ca0ee405 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -609,11 +609,11 @@ config SM_DISPCC_6125
> splash screen
>
> config SM_DISPCC_8250
> - tristate "SM8150 and SM8250 Display Clock Controller"
> + tristate "SM8150/SM8250/SM8350 Display Clock Controller"
> depends on SM_GCC_8150 || SM_GCC_8250
|| SM_GCC_8350?
sidenote: also || SC_GCC_8180X in a separate patch?
> help
> Support for the display clock controller on Qualcomm Technologies, Inc
> - SM8150 and SM8250 devices.
> + SM8150/SM8250/SM8350 devices.
> Say Y if you want to support display devices and functionality such as
> splash screen.
>
> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
> index db9379634fb2..8e6cb990e387 100644
> --- a/drivers/clk/qcom/dispcc-sm8250.c
> +++ b/drivers/clk/qcom/dispcc-sm8250.c
> @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = {
> { 249600000, 2000000000, 0 },
> };
>
> +static struct pll_vco lucid_5lpe_vco[] = {
> + { 249600000, 1750000000, 0 },
> +};
> +
> static struct alpha_pll_config disp_cc_pll0_config = {
> .l = 0x47,
> .alpha = 0xE000,
> @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = {
> { .compatible = "qcom,sc8180x-dispcc" },
> { .compatible = "qcom,sm8150-dispcc" },
> { .compatible = "qcom,sm8250-dispcc" },
> + { .compatible = "qcom,sm8350-dispcc" },
> { }
> };
> MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
> @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
> return PTR_ERR(regmap);
> }
>
> - /* note: trion == lucid, except for the prepare() op */
> + /* Apply differences for SM8150 and SM8350 */
> BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
> if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
> of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
> @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
> disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
> disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
> disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
> + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
> + static struct clk_rcg2 * const rcgs[] = {
> + &disp_cc_mdss_byte0_clk_src,
> + &disp_cc_mdss_byte1_clk_src,
> + &disp_cc_mdss_dp_aux1_clk_src,
> + &disp_cc_mdss_dp_aux_clk_src,
> + &disp_cc_mdss_dp_link1_clk_src,
> + &disp_cc_mdss_dp_link_clk_src,
> + &disp_cc_mdss_dp_pixel1_clk_src,
> + &disp_cc_mdss_dp_pixel2_clk_src,
> + &disp_cc_mdss_dp_pixel_clk_src,
> + &disp_cc_mdss_esc0_clk_src,
> + &disp_cc_mdss_mdp_clk_src,
> + &disp_cc_mdss_pclk0_clk_src,
> + &disp_cc_mdss_pclk1_clk_src,
> + &disp_cc_mdss_rot_clk_src,
> + &disp_cc_mdss_vsync_clk_src,
> + };
> + static struct clk_regmap_div * const divs[] = {
> + &disp_cc_mdss_byte0_div_clk_src,
> + &disp_cc_mdss_byte1_div_clk_src,
> + &disp_cc_mdss_dp_link1_div_clk_src,
> + &disp_cc_mdss_dp_link_div_clk_src,
> + };
> + unsigned int i;
> + static bool offset_applied;
> +
> + /* only apply the offsets once (in case of deferred probe) */
> + if (!offset_applied) {
> + for (i = 0; i < ARRAY_SIZE(rcgs); i++)
> + rcgs[i]->cmd_rcgr -= 4;
> +
> + for (i = 0; i < ARRAY_SIZE(divs); i++) {
> + divs[i]->reg -= 4;
> + divs[i]->width = 4;
> + }
> +
> + disp_cc_mdss_ahb_clk.halt_reg -= 4;
> + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
> +
> + offset_applied = true;
> + }
> +
> + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
> +
> + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
Lowercase hex, also below.
> + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
> + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> + disp_cc_pll0.vco_table = lucid_5lpe_vco;
> + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
> + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
> + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> + disp_cc_pll1.vco_table = lucid_5lpe_vco;
> }
>
> clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
Konrad
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC
2022-05-04 16:23 ` Konrad Dybcio
@ 2022-05-12 13:21 ` Robert Foss
0 siblings, 0 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-12 13:21 UTC (permalink / raw)
To: Konrad Dybcio
Cc: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
jonathan, tdas, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov
On Wed, 4 May 2022 at 18:23, Konrad Dybcio <konrad.dybcio@somainline.org> wrote:
>
>
> On 04/05/2022 14:27, Robert Foss wrote:
> > From: Jonathan Marek <jonathan@marek.ca>
> >
> > Add support to the SM8350 display clock controller by extending the SM8250
> > display clock controller, which is almost identical but has some minor
> > differences.
> >
> > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >
> > Changes since v1
> > - Remove comment - Dmitry
> >
> > Changes since v2
> > - Add my SoB - Bjorn
> > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag
> >
> >
> > drivers/clk/qcom/Kconfig | 4 +--
> > drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++-
> > 2 files changed, 61 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> > index 9b1f54e634b9..1752ca0ee405 100644
> > --- a/drivers/clk/qcom/Kconfig
> > +++ b/drivers/clk/qcom/Kconfig
> > @@ -609,11 +609,11 @@ config SM_DISPCC_6125
> > splash screen
> >
> > config SM_DISPCC_8250
> > - tristate "SM8150 and SM8250 Display Clock Controller"
> > + tristate "SM8150/SM8250/SM8350 Display Clock Controller"
> > depends on SM_GCC_8150 || SM_GCC_8250
>
> || SM_GCC_8350?
Will fix in v4.
>
> sidenote: also || SC_GCC_8180X in a separate patch?
I haven't been involved in the 8180X work, and am a little bit
hesitant to include any changes related to it in this series.
>
> > help
> > Support for the display clock controller on Qualcomm Technologies, Inc
> > - SM8150 and SM8250 devices.
> > + SM8150/SM8250/SM8350 devices.
> > Say Y if you want to support display devices and functionality such as
> > splash screen.
> >
> > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
> > index db9379634fb2..8e6cb990e387 100644
> > --- a/drivers/clk/qcom/dispcc-sm8250.c
> > +++ b/drivers/clk/qcom/dispcc-sm8250.c
> > @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = {
> > { 249600000, 2000000000, 0 },
> > };
> >
> > +static struct pll_vco lucid_5lpe_vco[] = {
> > + { 249600000, 1750000000, 0 },
> > +};
> > +
> > static struct alpha_pll_config disp_cc_pll0_config = {
> > .l = 0x47,
> > .alpha = 0xE000,
> > @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = {
> > { .compatible = "qcom,sc8180x-dispcc" },
> > { .compatible = "qcom,sm8150-dispcc" },
> > { .compatible = "qcom,sm8250-dispcc" },
> > + { .compatible = "qcom,sm8350-dispcc" },
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
> > @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
> > return PTR_ERR(regmap);
> > }
> >
> > - /* note: trion == lucid, except for the prepare() op */
> > + /* Apply differences for SM8150 and SM8350 */
> > BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
> > if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
> > of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
> > @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
> > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
> > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
> > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
> > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
> > + static struct clk_rcg2 * const rcgs[] = {
> > + &disp_cc_mdss_byte0_clk_src,
> > + &disp_cc_mdss_byte1_clk_src,
> > + &disp_cc_mdss_dp_aux1_clk_src,
> > + &disp_cc_mdss_dp_aux_clk_src,
> > + &disp_cc_mdss_dp_link1_clk_src,
> > + &disp_cc_mdss_dp_link_clk_src,
> > + &disp_cc_mdss_dp_pixel1_clk_src,
> > + &disp_cc_mdss_dp_pixel2_clk_src,
> > + &disp_cc_mdss_dp_pixel_clk_src,
> > + &disp_cc_mdss_esc0_clk_src,
> > + &disp_cc_mdss_mdp_clk_src,
> > + &disp_cc_mdss_pclk0_clk_src,
> > + &disp_cc_mdss_pclk1_clk_src,
> > + &disp_cc_mdss_rot_clk_src,
> > + &disp_cc_mdss_vsync_clk_src,
> > + };
> > + static struct clk_regmap_div * const divs[] = {
> > + &disp_cc_mdss_byte0_div_clk_src,
> > + &disp_cc_mdss_byte1_div_clk_src,
> > + &disp_cc_mdss_dp_link1_div_clk_src,
> > + &disp_cc_mdss_dp_link_div_clk_src,
> > + };
> > + unsigned int i;
> > + static bool offset_applied;
> > +
> > + /* only apply the offsets once (in case of deferred probe) */
> > + if (!offset_applied) {
> > + for (i = 0; i < ARRAY_SIZE(rcgs); i++)
> > + rcgs[i]->cmd_rcgr -= 4;
> > +
> > + for (i = 0; i < ARRAY_SIZE(divs); i++) {
> > + divs[i]->reg -= 4;
> > + divs[i]->width = 4;
> > + }
> > +
> > + disp_cc_mdss_ahb_clk.halt_reg -= 4;
> > + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
> > +
> > + offset_applied = true;
> > + }
> > +
> > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
> > +
> > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
>
> Lowercase hex, also below.
Ack.
>
>
> > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
> > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> > + disp_cc_pll0.vco_table = lucid_5lpe_vco;
> > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
> > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
> > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> > + disp_cc_pll1.vco_table = lucid_5lpe_vco;
> > }
> >
> > clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
> Konrad
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
2022-05-04 12:27 ` [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss
@ 2022-05-16 23:50 ` Rob Herring
2022-05-18 19:14 ` Robert Foss
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2022-05-16 23:50 UTC (permalink / raw)
To: Robert Foss
Cc: agross, bjorn.andersson, mturquette, sboyd, krzk+dt, jonathan,
tdas, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Dmitry Baryshkov, Dmitry Baryshkov
On Wed, May 04, 2022 at 02:27:22PM +0200, Robert Foss wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8350 SoCs.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
> include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++
> 2 files changed, 54 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> index 9ebcb1943b0a..4090cc7ea2ae 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> @@ -20,6 +20,7 @@ description: |
> dt-bindings/clock/qcom,gpucc-sm6350.h
> dt-bindings/clock/qcom,gpucc-sm8150.h
> dt-bindings/clock/qcom,gpucc-sm8250.h
> + dt-bindings/clock/qcom,gpucc-sm8350.h
>
> properties:
> compatible:
> @@ -31,6 +32,7 @@ properties:
> - qcom,sm6350-gpucc
> - qcom,sm8150-gpucc
> - qcom,sm8250-gpucc
> + - qcom,sm8350-gpucc
>
> clocks:
> items:
> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
> new file mode 100644
> index 000000000000..d2294e0d527e
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
QCom reviewed and approved the license on this, right?
Dual license.
> +/*
> + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
> +
> +/* GPU_CC clocks */
> +#define GPU_CC_AHB_CLK 0
> +#define GPU_CC_CB_CLK 1
> +#define GPU_CC_CRC_AHB_CLK 2
> +#define GPU_CC_CX_APB_CLK 3
> +#define GPU_CC_CX_GMU_CLK 4
> +#define GPU_CC_CX_QDSS_AT_CLK 5
> +#define GPU_CC_CX_QDSS_TRIG_CLK 6
> +#define GPU_CC_CX_QDSS_TSCTR_CLK 7
> +#define GPU_CC_CX_SNOC_DVM_CLK 8
> +#define GPU_CC_CXO_AON_CLK 9
> +#define GPU_CC_CXO_CLK 10
> +#define GPU_CC_FREQ_MEASURE_CLK 11
> +#define GPU_CC_GMU_CLK_SRC 12
> +#define GPU_CC_GX_GMU_CLK 13
> +#define GPU_CC_GX_QDSS_TSCTR_CLK 14
> +#define GPU_CC_GX_VSENSE_CLK 15
> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
> +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
> +#define GPU_CC_HUB_AON_CLK 18
> +#define GPU_CC_HUB_CLK_SRC 19
> +#define GPU_CC_HUB_CX_INT_CLK 20
> +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
> +#define GPU_CC_MND1X_0_GFX3D_CLK 22
> +#define GPU_CC_MND1X_1_GFX3D_CLK 23
> +#define GPU_CC_PLL0 24
> +#define GPU_CC_PLL1 25
> +#define GPU_CC_SLEEP_CLK 26
> +
> +/* GPU_CC resets */
> +#define GPUCC_GPU_CC_ACD_BCR 0
> +#define GPUCC_GPU_CC_CB_BCR 1
> +#define GPUCC_GPU_CC_CX_BCR 2
> +#define GPUCC_GPU_CC_FAST_HUB_BCR 3
> +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
> +#define GPUCC_GPU_CC_GMU_BCR 5
> +#define GPUCC_GPU_CC_GX_BCR 6
> +#define GPUCC_GPU_CC_XO_BCR 7
> +
> +/* GPU_CC GDSCRs */
> +#define GPU_CX_GDSC 0
> +#define GPU_GX_GDSC 1
> +
> +#endif
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
2022-05-16 23:50 ` Rob Herring
@ 2022-05-18 19:14 ` Robert Foss
0 siblings, 0 replies; 12+ messages in thread
From: Robert Foss @ 2022-05-18 19:14 UTC (permalink / raw)
To: Rob Herring
Cc: agross, bjorn.andersson, mturquette, sboyd, krzk+dt, jonathan,
tdas, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Dmitry Baryshkov, Dmitry Baryshkov
On Tue, 17 May 2022 at 01:50, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, May 04, 2022 at 02:27:22PM +0200, Robert Foss wrote:
> > Add device tree bindings for graphics clock controller for
> > Qualcomm Technology Inc's SM8350 SoCs.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org>
> > ---
> > .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 +
> > include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++
> > 2 files changed, 54 insertions(+)
> > create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> > index 9ebcb1943b0a..4090cc7ea2ae 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> > @@ -20,6 +20,7 @@ description: |
> > dt-bindings/clock/qcom,gpucc-sm6350.h
> > dt-bindings/clock/qcom,gpucc-sm8150.h
> > dt-bindings/clock/qcom,gpucc-sm8250.h
> > + dt-bindings/clock/qcom,gpucc-sm8350.h
> >
> > properties:
> > compatible:
> > @@ -31,6 +32,7 @@ properties:
> > - qcom,sm6350-gpucc
> > - qcom,sm8150-gpucc
> > - qcom,sm8250-gpucc
> > + - qcom,sm8350-gpucc
> >
> > clocks:
> > items:
> > diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
> > new file mode 100644
> > index 000000000000..d2294e0d527e
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
> > @@ -0,0 +1,52 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
>
> QCom reviewed and approved the license on this, right?
>
> Dual license.
Ah, yes. I'll change the license in v4 to:
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>
> > +/*
> > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
> > +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
> > +
> > +/* GPU_CC clocks */
> > +#define GPU_CC_AHB_CLK 0
> > +#define GPU_CC_CB_CLK 1
> > +#define GPU_CC_CRC_AHB_CLK 2
> > +#define GPU_CC_CX_APB_CLK 3
> > +#define GPU_CC_CX_GMU_CLK 4
> > +#define GPU_CC_CX_QDSS_AT_CLK 5
> > +#define GPU_CC_CX_QDSS_TRIG_CLK 6
> > +#define GPU_CC_CX_QDSS_TSCTR_CLK 7
> > +#define GPU_CC_CX_SNOC_DVM_CLK 8
> > +#define GPU_CC_CXO_AON_CLK 9
> > +#define GPU_CC_CXO_CLK 10
> > +#define GPU_CC_FREQ_MEASURE_CLK 11
> > +#define GPU_CC_GMU_CLK_SRC 12
> > +#define GPU_CC_GX_GMU_CLK 13
> > +#define GPU_CC_GX_QDSS_TSCTR_CLK 14
> > +#define GPU_CC_GX_VSENSE_CLK 15
> > +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
> > +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
> > +#define GPU_CC_HUB_AON_CLK 18
> > +#define GPU_CC_HUB_CLK_SRC 19
> > +#define GPU_CC_HUB_CX_INT_CLK 20
> > +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
> > +#define GPU_CC_MND1X_0_GFX3D_CLK 22
> > +#define GPU_CC_MND1X_1_GFX3D_CLK 23
> > +#define GPU_CC_PLL0 24
> > +#define GPU_CC_PLL1 25
> > +#define GPU_CC_SLEEP_CLK 26
> > +
> > +/* GPU_CC resets */
> > +#define GPUCC_GPU_CC_ACD_BCR 0
> > +#define GPUCC_GPU_CC_CB_BCR 1
> > +#define GPUCC_GPU_CC_CX_BCR 2
> > +#define GPUCC_GPU_CC_FAST_HUB_BCR 3
> > +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
> > +#define GPUCC_GPU_CC_GMU_BCR 5
> > +#define GPUCC_GPU_CC_GX_BCR 6
> > +#define GPUCC_GPU_CC_XO_BCR 7
> > +
> > +/* GPU_CC GDSCRs */
> > +#define GPU_CX_GDSC 0
> > +#define GPU_GX_GDSC 1
> > +
> > +#endif
> > --
> > 2.34.1
> >
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-05-18 19:14 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-04 12:27 [PATCH v3 0/6] SM8350 Display/GPU clock enablement Robert Foss
2022-05-04 12:27 ` [PATCH v3 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss
2022-05-04 12:27 ` [PATCH v3 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss
2022-05-04 13:34 ` Dmitry Baryshkov
2022-05-04 12:27 ` [PATCH v3 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss
2022-05-16 23:50 ` Rob Herring
2022-05-18 19:14 ` Robert Foss
2022-05-04 12:27 ` [PATCH v3 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss
2022-05-04 16:23 ` Konrad Dybcio
2022-05-12 13:21 ` Robert Foss
2022-05-04 12:27 ` [PATCH v3 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss
2022-05-04 12:27 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss
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