* [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers
@ 2022-05-10 5:53 Haoran Jiang
2022-05-10 7:45 ` Marc Zyngier
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Haoran Jiang @ 2022-05-10 5:53 UTC (permalink / raw)
To: chenhuacai; +Cc: jiaxun.yang, tglx, maz, linux-mips, linux-kernel, jianghaoran
According to the loongson cpu manual,different cpu cores
correspond to different interrupt status registers
Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
---
drivers/irqchip/irq-loongson-liointc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 649c58391618..f4e015b50af0 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -195,7 +195,7 @@ static int __init liointc_of_init(struct device_node *node,
}
for (i = 0; i < LIOINTC_NUM_CORES; i++)
- priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
+ priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
}
for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers
2022-05-10 5:53 [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers Haoran Jiang
@ 2022-05-10 7:45 ` Marc Zyngier
2022-05-10 8:08 ` Sergei Shtylyov
2022-05-10 12:15 ` Jiaxun Yang
2 siblings, 0 replies; 5+ messages in thread
From: Marc Zyngier @ 2022-05-10 7:45 UTC (permalink / raw)
To: Haoran Jiang; +Cc: chenhuacai, jiaxun.yang, tglx, linux-mips, linux-kernel
On 2022-05-10 06:53, Haoran Jiang wrote:
> According to the loongson cpu manual,different cpu cores
> correspond to different interrupt status registers
>
> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
> ---
> drivers/irqchip/irq-loongson-liointc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c
> b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct
> device_node *node,
> }
>
> for (i = 0; i < LIOINTC_NUM_CORES; i++)
> - priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> + priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
> }
>
> for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
You need to provide some more detail:
- where is it documented (something more precise than ¨the loongson cpu
manual¨)?
- if something doesn´t work today, what is the impact?
- why does it work today without this change?
- if this is a fix, what commit does it fix?
- if this is a fix, does it need to be backported to stable kernels?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers
2022-05-10 5:53 [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers Haoran Jiang
2022-05-10 7:45 ` Marc Zyngier
@ 2022-05-10 8:08 ` Sergei Shtylyov
2022-05-10 12:15 ` Jiaxun Yang
2 siblings, 0 replies; 5+ messages in thread
From: Sergei Shtylyov @ 2022-05-10 8:08 UTC (permalink / raw)
To: Haoran Jiang, chenhuacai; +Cc: jiaxun.yang, tglx, maz, linux-mips, linux-kernel
Hello!
On 5/10/22 8:53 AM, Haoran Jiang wrote:
> According to the loongson cpu manual,different cpu cores
Please add space after comma.
> correspond to different interrupt status registers
>
> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
> ---
> drivers/irqchip/irq-loongson-liointc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct device_node *node,
> }
>
> for (i = 0; i < LIOINTC_NUM_CORES; i++)
> - priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> + priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
Please add spaces around *.
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers
2022-05-10 5:53 [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers Haoran Jiang
2022-05-10 7:45 ` Marc Zyngier
2022-05-10 8:08 ` Sergei Shtylyov
@ 2022-05-10 12:15 ` Jiaxun Yang
2022-05-11 5:33 ` jianghaoran
2 siblings, 1 reply; 5+ messages in thread
From: Jiaxun Yang @ 2022-05-10 12:15 UTC (permalink / raw)
To: Haoran Jiang, chenhuacai; +Cc: tglx, maz, linux-mips, linux-kernel
在 2022/5/10 6:53, Haoran Jiang 写道:
> According to the loongson cpu manual,different cpu cores
> correspond to different interrupt status registers
NAK!
It is intentional to do so.
The per-core ISR register is broken on 3B1500. So we use general ISR
register here.
The per-core variable is left for LS2K.
Thanks
- Jiaxun
>
> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
> ---
> drivers/irqchip/irq-loongson-liointc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 649c58391618..f4e015b50af0 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct device_node *node,
> }
>
> for (i = 0; i < LIOINTC_NUM_CORES; i++)
> - priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> + priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
> }
>
> for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers
2022-05-10 12:15 ` Jiaxun Yang
@ 2022-05-11 5:33 ` jianghaoran
0 siblings, 0 replies; 5+ messages in thread
From: jianghaoran @ 2022-05-11 5:33 UTC (permalink / raw)
To: Jiaxun Yang, chenhuacai; +Cc: tglx, maz, linux-mips, linux-kernel
在 2022/5/10 下午8:15, Jiaxun Yang 写道:
>
>
> 在 2022/5/10 6:53, Haoran Jiang 写道:
>> According to the loongson cpu manual,different cpu cores
>> correspond to different interrupt status registers
> NAK!
>
> It is intentional to do so.
>
> The per-core ISR register is broken on 3B1500. So we use general ISR
> register here.
> The per-core variable is left for LS2K.
>
> Thanks
> - Jiaxun
>>
>> Signed-off-by: Haoran Jiang <jianghaoran@kylinos.cn>
>> ---
>> drivers/irqchip/irq-loongson-liointc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/irqchip/irq-loongson-liointc.c
>> b/drivers/irqchip/irq-loongson-liointc.c
>> index 649c58391618..f4e015b50af0 100644
>> --- a/drivers/irqchip/irq-loongson-liointc.c
>> +++ b/drivers/irqchip/irq-loongson-liointc.c
>> @@ -195,7 +195,7 @@ static int __init liointc_of_init(struct
>> device_node *node,
>> }
>> for (i = 0; i < LIOINTC_NUM_CORES; i++)
>> - priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
>> + priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS + i*8;
>> }
>> for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
>
Thank you for your review!
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-05-11 5:36 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 5:53 [PATCH] irqchip/loongson-liointc: 4 cores correspond to different interrupt status registers Haoran Jiang
2022-05-10 7:45 ` Marc Zyngier
2022-05-10 8:08 ` Sergei Shtylyov
2022-05-10 12:15 ` Jiaxun Yang
2022-05-11 5:33 ` jianghaoran
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).