* [PATCH v3 0/3] MediaTek MT8195 display binding
@ 2022-05-12 8:05 Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-12 8:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Rex-BC Chen
Add this series to present MediaTek display binding for MT8195.
The reason I send this series is Jason and Nancy's binding patches are
never received by devicetree mail server.
Therefore, I help them to resend binding patches.
Changes for v3:
1. Fix rdma and ethdr binding doc.
2. Nancy's series: [1].
3. This series is based on linux-next: next-20220511.
Changes for v2:
1. This patch is based on linux next-20220506.
2. Jason's patches are accepted and I drop them.
[1]: https://lore.kernel.org/all/20220512053128.31415-1-nancy.lin@mediatek.com/
Nancy.Lin (3):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: reset: mt8195: add vdosys1 reset control bit
dt-bindings: mediatek: add ethdr definition for mt8195
.../display/mediatek/mediatek,ethdr.yaml | 188 ++++++++++++++++++
.../display/mediatek/mediatek,mdp-rdma.yaml | 88 ++++++++
include/dt-bindings/reset/mt8195-resets.h | 45 +++++
3 files changed, 321 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
--
2.18.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
2022-05-12 8:05 [PATCH v3 0/3] MediaTek MT8195 display binding Rex-BC Chen
@ 2022-05-12 8:05 ` Rex-BC Chen
2022-05-13 8:30 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
2022-05-12 8:05 ` [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
2 siblings, 2 replies; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-12 8:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..678abb321cc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MDP RDMA
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ The MediaTek MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+ #include <dt-bindings/memory/mt8195-memory-port.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2022-05-12 8:05 [PATCH v3 0/3] MediaTek MT8195 display binding Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
@ 2022-05-12 8:05 ` Rex-BC Chen
2022-05-13 8:30 ` Krzysztof Kozlowski
2022-05-12 8:05 ` [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
2 siblings, 1 reply; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-12 8:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..1ccfe2f28964 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,49 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
+#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
+#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
+#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
+#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
+#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
+#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195
2022-05-12 8:05 [PATCH v3 0/3] MediaTek MT8195 display binding Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit Rex-BC Chen
@ 2022-05-12 8:05 ` Rex-BC Chen
2022-05-13 8:31 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
2 siblings, 2 replies; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-12 8:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
From: "Nancy.Lin" <nancy.lin@mediatek.com>
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 188 ++++++++++++++++++
1 file changed, 188 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..be81d8873354
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,188 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Ethdr Device
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
+ designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color
+ space/color format conversion, and then combine different layers,
+ output the required HDR or SDR signal to the subsequent display path.
+ This engine is composed of two video frontends, two graphic frontends,
+ one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
+ These two function blocks read the pre-programmed registers from DRAM and
+ set them to HW in the v-blanking period.
+
+properties:
+ compatible:
+ - const: mediatek,mt8195-disp-ethdr
+
+ reg:
+ maxItems: 7
+
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: video frontend 0 async reset
+ - description: video frontend 1 async reset
+ - description: graphic frontend 0 async reset
+ - description: graphic frontend 1 async reset
+ - description: video backend async reset
+
+ reset-names:
+ items:
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
+ function block.
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ minItems: 7
+ maxItems: 7
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+ - resets
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+ #include <dt-bindings/memory/mt8195-memory-port.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ #include <dt-bindings/reset/mt8195-resets.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hdr-engine@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11a000 0 0x1000>,
+ <0 0x1c11b000 0 0x1000>,
+ <0 0x1c11c000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
+ "gfx_fe1_async", "vdo_be_async";
+ };
+ };
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
@ 2022-05-13 8:30 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 8:30 UTC (permalink / raw)
To: Rex-BC Chen, robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 12/05/2022 10:05, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 RDMA definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2022-05-12 8:05 ` [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit Rex-BC Chen
@ 2022-05-13 8:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 8:30 UTC (permalink / raw)
To: Rex-BC Chen, robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 12/05/2022 10:05, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 reset control bit for MT8195 platform.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195
2022-05-12 8:05 ` [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
@ 2022-05-13 8:31 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 8:31 UTC (permalink / raw)
To: Rex-BC Chen, robh+dt, krzysztof.kozlowski+dt, chunkuang.hu, p.zabel
Cc: airlied, matthias.bgg, angelogioacchino.delregno, jason-jh.lin,
nancy.lin, devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 12/05/2022 10:05, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
2022-05-13 8:30 ` Krzysztof Kozlowski
@ 2022-05-13 12:33 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-05-13 12:33 UTC (permalink / raw)
To: Rex-BC Chen
Cc: linux-arm-kernel, Project_Global_Chrome_Upstream_Group, p.zabel,
matthias.bgg, linux-mediatek, robh+dt, krzysztof.kozlowski+dt,
angelogioacchino.delregno, devicetree, linux-kernel, airlied,
nancy.lin, dri-devel, chunkuang.hu, jason-jh.lin
On Thu, 12 May 2022 16:05:21 +0800, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 RDMA definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../display/mediatek/mediatek,mdp-rdma.yaml | 88 +++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml: properties:compatible: [{'const': 'mediatek,mt8195-vdo1-rdma'}] is not of type 'object', 'boolean'
from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.example.dts:25:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory
25 | #include <dt-bindings/memory/mt8195-memory-port.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195
2022-05-12 8:05 ` [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
2022-05-13 8:31 ` Krzysztof Kozlowski
@ 2022-05-13 12:33 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-05-13 12:33 UTC (permalink / raw)
To: Rex-BC Chen
Cc: Project_Global_Chrome_Upstream_Group, linux-kernel,
linux-arm-kernel, nancy.lin, krzysztof.kozlowski+dt, devicetree,
airlied, robh+dt, p.zabel, matthias.bgg, chunkuang.hu,
angelogioacchino.delregno, jason-jh.lin, linux-mediatek,
dri-devel
On Thu, 12 May 2022 16:05:23 +0800, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 188 ++++++++++++++++++
> 1 file changed, 188 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml: properties:compatible: [{'const': 'mediatek,mt8195-disp-ethdr'}] is not of type 'object', 'boolean'
from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:24:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory
24 | #include <dt-bindings/memory/mt8195-memory-port.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-05-13 12:33 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-12 8:05 [PATCH v3 0/3] MediaTek MT8195 display binding Rex-BC Chen
2022-05-12 8:05 ` [PATCH v3 1/3] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
2022-05-13 8:30 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
2022-05-12 8:05 ` [PATCH v3 2/3] dt-bindings: reset: mt8195: add vdosys1 reset control bit Rex-BC Chen
2022-05-13 8:30 ` Krzysztof Kozlowski
2022-05-12 8:05 ` [PATCH v3 3/3] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
2022-05-13 8:31 ` Krzysztof Kozlowski
2022-05-13 12:33 ` Rob Herring
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