From: Sheng Bi <windy.bi.enflame@gmail.com>
To: helgaas@kernel.org, bhelgaas@google.com
Cc: alex.williamson@redhat.com, lukas@wunner.de,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Sheng Bi <windy.bi.enflame@gmail.com>
Subject: [PATCH v2] PCI: Fix no-op wait after secondary bus reset
Date: Wed, 18 May 2022 19:54:32 +0800 [thread overview]
Message-ID: <20220518115432.76183-1-windy.bi.enflame@gmail.com> (raw)
In-Reply-To: <20220516165740.6256af51.alex.williamson@redhat.com>
pci_bridge_secondary_bus_reset() triggers SBR followed by 1 second sleep,
and then uses pci_dev_wait() for waiting device ready. The dev parameter
passes to the wait function is currently the bridge itself, but not the
device been reset.
If we call pci_bridge_secondary_bus_reset() to trigger SBR to a device,
there is 1 second sleep but not waiting device ready, since the bridge
is always ready while resetting downstream devices. pci_dev_wait() here
is a no-op actually. This would be risky in the case which the device
becomes ready after more than 1 second, especially while hotplug enabled.
The late coming hotplug event after 1 second will trigger hotplug module
to remove/re-insert the device.
Instead of waiting ready of bridge itself, changing to wait all the
downstream devices become ready with timeout PCIE_RESET_READY_POLL_MS
after SBR, considering all downstream devices are affected during SBR.
Once one of the devices doesn't reappear within the timeout, return
-ENOTTY to indicate SBR doesn't complete successfully.
Fixes: 6b2f1351af56 ("PCI: Wait for device to become ready after secondary bus reset")
Signed-off-by: Sheng Bi <windy.bi.enflame@gmail.com>
---
drivers/pci/pci.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index eb7c0a08ff57..32b7a5c1fa3a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5049,6 +5049,34 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
}
}
+static int pci_bridge_secondary_bus_wait(struct pci_dev *bridge, int timeout)
+{
+ struct pci_dev *dev;
+ int delay = 0;
+
+ if (!bridge->subordinate || list_empty(&bridge->subordinate->devices))
+ return 0;
+
+ list_for_each_entry(dev, &bridge->subordinate->devices, bus_list) {
+ while (!pci_device_is_present(dev)) {
+ if (delay > timeout) {
+ pci_warn(dev, "not ready %dms after secondary bus reset; giving up\n",
+ delay);
+ return -ENOTTY;
+ }
+
+ msleep(20);
+ delay += 20;
+ }
+
+ if (delay > 1000)
+ pci_info(dev, "ready %dms after secondary bus reset\n",
+ delay);
+ }
+
+ return 0;
+}
+
void pci_reset_secondary_bus(struct pci_dev *dev)
{
u16 ctrl;
@@ -5092,7 +5120,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
{
pcibios_reset_secondary_bus(dev);
- return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
+ return pci_bridge_secondary_bus_wait(dev, PCIE_RESET_READY_POLL_MS);
}
EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
base-commit: 617c8a1e527fadaaec3ba5bafceae7a922ebef7e
--
2.36.1
next prev parent reply other threads:[~2022-05-18 11:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 17:30 [PATCH] drivers/pci: wait downstream hierarchy ready instead of slot itself ready, after secondary bus reset windy.bi.enflame
2022-05-16 20:28 ` Bjorn Helgaas
2022-05-16 22:57 ` Alex Williamson
2022-05-17 14:56 ` windy Bi
2022-05-18 11:54 ` Sheng Bi [this message]
2022-05-19 17:06 ` [PATCH v2] PCI: Fix no-op wait " Alex Williamson
2022-05-20 3:00 ` windy Bi
2022-05-20 6:41 ` Lukas Wunner
2022-05-21 8:36 ` Sheng Bi
2022-05-21 12:49 ` Lukas Wunner
2022-05-21 17:37 ` Sheng Bi
2022-05-23 14:20 ` Lukas Wunner
2022-05-23 15:59 ` Sheng Bi
2022-05-23 17:15 ` [PATCH v3] " Sheng Bi
2022-06-08 13:16 ` Sheng Bi
2022-06-08 15:23 ` Lukas Wunner
2022-05-17 5:34 ` [PATCH] drivers/pci: wait downstream hierarchy ready instead of slot itself ready, " kernel test robot
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