From: Sheng Bi <windy.bi.enflame@gmail.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Alex Williamson <alex.williamson@redhat.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: Fix no-op wait after secondary bus reset
Date: Mon, 23 May 2022 23:59:23 +0800 [thread overview]
Message-ID: <CAGdb+H0qnC4noBa_=N3oQW88+dgXYtA7gqJ5qiD2g7Ywd+2K=Q@mail.gmail.com> (raw)
In-Reply-To: <20220523142042.GA19286@wunner.de>
On Mon, May 23, 2022 at 10:20 PM Lukas Wunner <lukas@wunner.de> wrote:
>
> On Sun, May 22, 2022 at 01:37:50AM +0800, Sheng Bi wrote:
> > On Sat, May 21, 2022 at 8:49 PM Lukas Wunner <lukas@wunner.de> wrote:
> > > On Sat, May 21, 2022 at 04:36:10PM +0800, Sheng Bi wrote:
> > > > If so, I also want to align the polling things mentioned in the
> > > > question from Alex, since pci_dev_wait() is also used for reset
> > > > functions other than SBR. To Bjorn, Alex, Lucas, how do you think if
> > > > we need to change the polling in pci_dev_wait() to 20ms intervals, or
> > > > keep binary exponential back-off with probable unexpected extra
> > > > timeout delay.
> > >
> > > The exponential backoff should probably be capped at some point
> > > to avoid excessive wait delays. I guess the rationale for
> > > exponential backoff is to not poll too frequently.
> > > Capping at 20 msec or 100 msec may be reasonable, i.e.:
> > >
> > > - delay *= 2;
> > > + delay = min(delay * 2, 100);
> >
> > Capping at 20 or 100 msec seems reasonable to me. Btw, since 20 msec
> > is not a long time in these scenarios, how about changing to a fixed
> > 20 msec interval?
>
> The callers of pci_dev_wait() seem to wait for the spec-defined
> delay and only call pci_dev_wait() to allow for an additional period
> that non-compliant devices may need. That extra delay can be expected
> to be low, which is why it makes sense to start with a short poll interval
> and gradually extend it. So the algorithm seems to be reasonable and
> I wouldn't recommend changing it to a constant interval unless that
> fixes something which is currently broken.
>
> Thanks,
>
> Lukas
Thanks Lukas!
From my perspective, there is nothing broken so far, but a theoretical
unexpected extra delay while the timeout has passed. So I will keep
pci_dev_wait() as previously with exponential backoff in this patch,
and change the pci_bridge_secondary_bus_wait() with "jiffies" and
pci_dev_wait().
Thanks,
windy
next prev parent reply other threads:[~2022-05-23 15:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 17:30 [PATCH] drivers/pci: wait downstream hierarchy ready instead of slot itself ready, after secondary bus reset windy.bi.enflame
2022-05-16 20:28 ` Bjorn Helgaas
2022-05-16 22:57 ` Alex Williamson
2022-05-17 14:56 ` windy Bi
2022-05-18 11:54 ` [PATCH v2] PCI: Fix no-op wait " Sheng Bi
2022-05-19 17:06 ` Alex Williamson
2022-05-20 3:00 ` windy Bi
2022-05-20 6:41 ` Lukas Wunner
2022-05-21 8:36 ` Sheng Bi
2022-05-21 12:49 ` Lukas Wunner
2022-05-21 17:37 ` Sheng Bi
2022-05-23 14:20 ` Lukas Wunner
2022-05-23 15:59 ` Sheng Bi [this message]
2022-05-23 17:15 ` [PATCH v3] " Sheng Bi
2022-06-08 13:16 ` Sheng Bi
2022-06-08 15:23 ` Lukas Wunner
2022-05-17 5:34 ` [PATCH] drivers/pci: wait downstream hierarchy ready instead of slot itself ready, " kernel test robot
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