* [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g
@ 2022-05-22 5:48 Jiaqing Zhao
2022-05-22 5:48 ` [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g Jiaqing Zhao
2022-05-23 7:54 ` [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Michael Walle
0 siblings, 2 replies; 5+ messages in thread
From: Jiaqing Zhao @ 2022-05-22 5:48 UTC (permalink / raw)
To: linux-mtd, Tudor Ambarus, Pratyush Yadav, Michael Walle
Cc: linux-kernel, Jiaqing Zhao
Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
x1, x2, and x4 operation modes.
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
---
drivers/mtd/spi-nor/macronix.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index d81a4cb2812b..1c45829be5ef 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -95,6 +95,9 @@ static const struct flash_info macronix_nor_parts[] = {
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
+ { "mx66l2g45g", INFO(0xc2201c, 0, 64 * 1024, 4096)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048)
NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096)
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g
2022-05-22 5:48 [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Jiaqing Zhao
@ 2022-05-22 5:48 ` Jiaqing Zhao
2022-07-21 7:59 ` Tudor.Ambarus
2022-05-23 7:54 ` [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Michael Walle
1 sibling, 1 reply; 5+ messages in thread
From: Jiaqing Zhao @ 2022-05-22 5:48 UTC (permalink / raw)
To: linux-mtd, Tudor Ambarus, Pratyush Yadav, Michael Walle
Cc: linux-kernel, Jiaqing Zhao
The Micron mt25ql02g supports x2 width dual mode operation. This patch
adds the SPI_NOR_DUAL_READ flag to its flash_info entry.
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
---
drivers/mtd/spi-nor/micron-st.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 8a20475ce77a..da0251c1a263 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -233,7 +233,7 @@ static const struct flash_info st_nor_parts[] = {
},
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
FLAGS(NO_CHIP_ERASE)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
MFR_FLAGS(USE_FSR)
},
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g
2022-05-22 5:48 ` [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g Jiaqing Zhao
@ 2022-07-21 7:59 ` Tudor.Ambarus
0 siblings, 0 replies; 5+ messages in thread
From: Tudor.Ambarus @ 2022-07-21 7:59 UTC (permalink / raw)
To: jiaqing.zhao, linux-mtd, p.yadav, michael; +Cc: linux-kernel
On 5/22/22 08:48, Jiaqing Zhao wrote:
> [You don't often get email from jiaqing.zhao@linux.intel.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification.]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The Micron mt25ql02g supports x2 width dual mode operation. This patch
> adds the SPI_NOR_DUAL_READ flag to its flash_info entry.
can't the dual mode be retrieved from SFDP?
Can you dump the sysfs sfdp table please?
>
> Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
> ---
> drivers/mtd/spi-nor/micron-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 8a20475ce77a..da0251c1a263 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -233,7 +233,7 @@ static const struct flash_info st_nor_parts[] = {
> },
> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
> FLAGS(NO_CHIP_ERASE)
> - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
> + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> MFR_FLAGS(USE_FSR)
> },
> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g
2022-05-22 5:48 [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Jiaqing Zhao
2022-05-22 5:48 ` [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g Jiaqing Zhao
@ 2022-05-23 7:54 ` Michael Walle
[not found] ` <b3e85d41-9415-b911-6f61-941885af1955@linux.intel.com>
1 sibling, 1 reply; 5+ messages in thread
From: Michael Walle @ 2022-05-23 7:54 UTC (permalink / raw)
To: Jiaqing Zhao; +Cc: linux-mtd, Tudor Ambarus, Pratyush Yadav, linux-kernel
Hi,
Am 2022-05-22 07:48, schrieb Jiaqing Zhao:
> Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
> x1, x2, and x4 operation modes.
I presume this one supports SFDP? Please provide an SFDP dump, see [1].
If it supports SFDP please try to use the SNOR_ID3() macro [2].
Also please add what was tested in your commit message.
Same goes for your patch 2/2.
-michael
[1]
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/
[2]
https://lore.kernel.org/linux-mtd/20220510140232.3519184-1-michael@walle.cc/
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-07-21 8:00 UTC | newest]
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2022-05-22 5:48 [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Jiaqing Zhao
2022-05-22 5:48 ` [PATCH 2/2] mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25ql02g Jiaqing Zhao
2022-07-21 7:59 ` Tudor.Ambarus
2022-05-23 7:54 ` [PATCH 1/2] mtd: spi-nor: macronix: Add support for mx66l2g45g Michael Walle
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2022-05-23 12:18 ` Jiaqing Zhao
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