From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<nfraprado@collabora.com>, <chun-jie.chen@mediatek.com>,
<wenst@chromium.org>, <runyang.chen@mediatek.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [RESEND v8 10/19] clk: mediatek: reset: Add new register reset function with device
Date: Mon, 23 May 2022 17:33:37 +0800 [thread overview]
Message-ID: <20220523093346.28493-11-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com>
Using device to register reset controller is a better implementation in
current drivers. Howerver, some clock drviers of MediaTek only provide
device_node.
Therefore, we still remain the register reset function with device_node
and add a new function with device to register reset controller.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/clk/mediatek/clk-mt2701-eth.c | 2 +-
drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 2 +-
drivers/clk/mediatek/clk-mt2701.c | 4 +-
drivers/clk/mediatek/clk-mt2712.c | 4 +-
drivers/clk/mediatek/clk-mt7622-eth.c | 2 +-
drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-
drivers/clk/mediatek/clk-mt7622.c | 4 +-
drivers/clk/mediatek/clk-mt7629-eth.c | 2 +-
drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-
drivers/clk/mediatek/clk-mt8183.c | 2 +-
drivers/clk/mediatek/reset.c | 60 +++++++++++++++++++++++++++
drivers/clk/mediatek/reset.h | 10 +++++
13 files changed, 86 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index b4e7f38860d0..edf1e2ed2b59 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -66,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 1431fa76a0f8..1458109d99d9 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -60,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 60bda56a102c..434cbbe8c037 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -65,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
return r;
}
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return 0;
}
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 6c7a80fb4349..9b442af37e67 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -805,7 +805,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
if (r)
return r;
- mtk_register_reset_controller(node, &clk_rst_desc[0]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return 0;
}
@@ -928,7 +928,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
if (r)
return r;
- mtk_register_reset_controller(node, &clk_rst_desc[1]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return 0;
}
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index fd310c375fdf..56980dd6c2ea 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1379,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, &clk_rst_desc[0]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return r;
}
@@ -1401,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, &clk_rst_desc[1]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index 90d55f882215..43de0477d5d9 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -90,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 489b64725b22..67e96231dd25 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -101,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
@@ -123,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0cba74d38499..3b55f8641fae 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -681,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
if (r)
return r;
- mtk_register_reset_controller(node, &clk_rst_desc[0]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return 0;
}
@@ -732,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
- mtk_register_reset_controller(node, &clk_rst_desc[1]);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return 0;
}
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 11b346c9d916..282dd6559465 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -100,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index c0583043710f..0c8b9e139789 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -96,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
@@ -118,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 5bc738f4d0e7..b1d810f85b71 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1256,7 +1256,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
return r;
}
- mtk_register_reset_controller(node, &clk_rst_desc);
+ mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index b9718f0f9d16..179505549a7c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -169,4 +169,64 @@ int mtk_register_reset_controller(struct device_node *np,
return 0;
}
+int mtk_register_reset_controller_with_dev(struct device *dev,
+ const struct mtk_clk_rst_desc *desc)
+{
+ struct device_node *np = dev->of_node;
+ struct regmap *regmap;
+ const struct reset_control_ops *rcops = NULL;
+ struct mtk_clk_rst_data *data;
+ int ret;
+
+ if (!desc) {
+ dev_err(dev, "mtk clock reset desc is NULL\n");
+ return -EINVAL;
+ }
+
+ switch (desc->version) {
+ case MTK_RST_SIMPLE:
+ rcops = &mtk_reset_ops;
+ break;
+ case MTK_RST_SET_CLR:
+ rcops = &mtk_reset_ops_set_clr;
+ break;
+ default:
+ dev_err(dev, "Unknown reset version %d\n", desc->version);
+ return -EINVAL;
+ }
+
+ regmap = device_node_to_regmap(np);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Cannot find regmap %pe\n", regmap);
+ return -EINVAL;
+ }
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ data->regmap = regmap;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = rcops;
+ data->rcdev.of_node = np;
+ data->rcdev.dev = dev;
+
+ if (data->desc->rst_idx_map_nr > 0) {
+ data->rcdev.of_reset_n_cells = 1;
+ data->rcdev.nr_resets = desc->rst_idx_map_nr;
+ data->rcdev.of_xlate = reset_xlate;
+ } else {
+ data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
+ }
+
+ ret = devm_reset_controller_register(dev, &data->rcdev);
+ if (ret) {
+ dev_err(dev, "could not register reset controller: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 260f25f27656..f7e1f31e3946 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -62,4 +62,14 @@ struct mtk_clk_rst_data {
int mtk_register_reset_controller(struct device_node *np,
const struct mtk_clk_rst_desc *desc);
+/**
+ * mtk_register_reset_controller - Register mediatek clock reset controller with device
+ * @np: Pointer to device.
+ * @desc: Constant pointer to description of clock reset.
+ *
+ * Return: 0 on success and errorno otherwise.
+ */
+int mtk_register_reset_controller_with_dev(struct device *dev,
+ const struct mtk_clk_rst_desc *desc);
+
#endif /* __DRV_CLK_MTK_RESET_H */
--
2.18.0
next prev parent reply other threads:[~2022-05-23 9:34 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 9:33 [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 01/19] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 02/19] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 03/19] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 04/19] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 05/19] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 06/19] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 08/19] clk: mediatek: reset: Support inuput argument index mode Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 09/19] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-06-16 1:52 ` Stephen Boyd
2022-05-23 9:33 ` Rex-BC Chen [this message]
2022-06-16 1:52 ` [RESEND v8 10/19] clk: mediatek: reset: Add new register reset function with device Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 11/19] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index " Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 14/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 17/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 18/19] dt-bindings: arm: mediatek: Add #reset-cells property " Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 19/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 10:28 ` [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs AngeloGioacchino Del Regno
2022-06-13 5:26 ` Rex-BC Chen
2022-06-16 1:57 ` Stephen Boyd
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