From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<nfraprado@collabora.com>, <chun-jie.chen@mediatek.com>,
<wenst@chromium.org>, <runyang.chen@mediatek.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [RESEND v8 14/19] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
Date: Mon, 23 May 2022 17:33:41 +0800 [thread overview]
Message-ID: <20220523093346.28493-15-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com>
The infra_ao reset is needed for MT8192 and MT8195.
- Add mtk_clk_rst_desc for MT8192 and MT8195
- Add register reset controller function for MT8192 infra_ao.
- Move definition of infra reset from cl-mt8183.c to reset.h
because it's the same definition with MT8192 and MT8195.
- Add new definition of infra reset_4 for MT8192 and MT8195.
- Add infra_ao_idx_map for MT8192 and MT8195.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[Nícolas: Test for MT8192]
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
drivers/clk/mediatek/clk-mt8183.c | 6 -----
drivers/clk/mediatek/clk-mt8192.c | 29 ++++++++++++++++++++++
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 24 ++++++++++++++++++
drivers/clk/mediatek/reset.h | 7 ++++++
4 files changed, 60 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index b1d810f85b71..8512101e1189 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -18,12 +18,6 @@
#include <dt-bindings/clock/mt8183-clk.h>
-/* Infra global controller reset set register */
-#define INFRA_RST0_SET_OFFSET 0x120
-#define INFRA_RST1_SET_OFFSET 0x130
-#define INFRA_RST2_SET_OFFSET 0x140
-#define INFRA_RST3_SET_OFFSET 0x150
-
static DEFINE_SPINLOCK(mt8183_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index dda211b7a745..ebbd2798d9a3 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -18,6 +18,7 @@
#include "clk-pll.h"
#include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/reset/mt8192-resets.h>
static DEFINE_SPINLOCK(mt8192_clk_lock);
@@ -1114,6 +1115,30 @@ static const struct mtk_gate top_clks[] = {
GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
};
+static u16 infra_ao_rst_ofs[] = {
+ INFRA_RST0_SET_OFFSET,
+ INFRA_RST1_SET_OFFSET,
+ INFRA_RST2_SET_OFFSET,
+ INFRA_RST3_SET_OFFSET,
+ INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+ [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+ [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
+ [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
+ [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
+ [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
+};
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = infra_ao_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+ .rst_idx_map = infra_ao_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
#define MT8192_PLL_FMAX (3800UL * MHZ)
#define MT8192_PLL_FMIN (1500UL * MHZ)
#define MT8192_INTEGER_BITS 8
@@ -1240,6 +1265,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
if (r)
goto free_clk_data;
+ r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+ if (r)
+ goto free_clk_data;
+
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..97657f255618 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -7,6 +7,7 @@
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
@@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] = {
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
};
+static u16 infra_ao_rst_ofs[] = {
+ INFRA_RST0_SET_OFFSET,
+ INFRA_RST1_SET_OFFSET,
+ INFRA_RST2_SET_OFFSET,
+ INFRA_RST3_SET_OFFSET,
+ INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+ [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+ [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
+ [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
+};
+
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = infra_ao_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+ .rst_idx_map = infra_ao_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
+ .rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index f7e1f31e3946..6a58a3d59165 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -11,6 +11,13 @@
#define RST_NR_PER_BANK 32
+/* Infra global controller reset set register */
+#define INFRA_RST0_SET_OFFSET 0x120
+#define INFRA_RST1_SET_OFFSET 0x130
+#define INFRA_RST2_SET_OFFSET 0x140
+#define INFRA_RST3_SET_OFFSET 0x150
+#define INFRA_RST4_SET_OFFSET 0x730
+
/**
* enum mtk_reset_version - Version of MediaTek clock reset controller.
* @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
--
2.18.0
next prev parent reply other threads:[~2022-05-23 9:36 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 9:33 [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 01/19] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 02/19] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 03/19] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 04/19] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-06-16 1:50 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 05/19] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 06/19] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 08/19] clk: mediatek: reset: Support inuput argument index mode Rex-BC Chen
2022-06-16 1:51 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 09/19] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-06-16 1:52 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 10/19] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-06-16 1:52 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 11/19] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index " Rex-BC Chen
2022-06-16 1:53 ` Stephen Boyd
2022-05-23 9:33 ` Rex-BC Chen [this message]
2022-06-16 1:55 ` [RESEND v8 14/19] clk: mediatek: reset: Add infra_ao reset support " Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-05-23 9:33 ` [RESEND v8 17/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 18/19] dt-bindings: arm: mediatek: Add #reset-cells property " Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 9:33 ` [RESEND v8 19/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-06-16 1:55 ` Stephen Boyd
2022-05-23 10:28 ` [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs AngeloGioacchino Del Regno
2022-06-13 5:26 ` Rex-BC Chen
2022-06-16 1:57 ` Stephen Boyd
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