* [PATCH v4 0/5] Add Chameleon v3 devicetree
@ 2022-06-03 9:23 Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Paweł Anikiel
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel
The Google Chameleon v3 is a board made for testing both video and audio
interfaces of external devices. It acts as a base board for the
Mercury+ AA1 module.
socfpga_arria10_mercury_aa1.dtsi and socfpga_arria10_chameleonv3.dts
have also been sent to u-boot:
https://lists.denx.de/pipermail/u-boot/2022-May/485107.html
https://lists.denx.de/pipermail/u-boot/2022-May/485111.html
v4 changes:
- remove enclustra,mercury-aa1 from Arria 10 boards in dt-bindings
v3 changes:
- make seperate group for Chameleon v3 in dt-bindings
- add blank line after copyright header
v2 changes:
- split first patch into three
- move sdmmc-ecc node to socfpga_arria10.dtsi (instead of removing it entirely)
- use generic names for dts node names
- keep the enclustra,mercury-aa1 compatible
Paweł Anikiel (5):
ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
ARM: dts: socfpga: Add Google Chameleon v3 devicetree
dt-bindings: altera: Add Chameleon v3 board
.../devicetree/bindings/arm/altera.yaml | 9 +-
arch/arm/boot/dts/Makefile | 2 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 10 +++
.../boot/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++
...1.dts => socfpga_arria10_mercury_aa1.dtsi} | 48 ++--------
5 files changed, 117 insertions(+), 42 deletions(-)
create mode 100644 arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
rename arch/arm/boot/dts/{socfpga_arria10_mercury_aa1.dts => socfpga_arria10_mercury_aa1.dtsi} (70%)
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
@ 2022-06-03 9:23 ` Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts Paweł Anikiel
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel, Krzysztof Kozlowski
The Mercury+ AA1 is not a standalone board, rather it's a module
with an Arria 10 SoC. Remove status = "okay" and i2c aliases, as they
are routed to the base board and should be enabled from there.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/Makefile | 1 -
...1.dts => socfpga_arria10_mercury_aa1.dtsi} | 28 -------------------
2 files changed, 29 deletions(-)
rename arch/arm/boot/dts/{socfpga_arria10_mercury_aa1.dts => socfpga_arria10_mercury_aa1.dtsi} (84%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index edfbedaa6168..023c8b4ba45c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1146,7 +1146,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
- socfpga_arria10_mercury_aa1.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
similarity index 84%
rename from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
rename to arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index a75c059b6727..4b21351f2694 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
#include "socfpga_arria10.dtsi"
@@ -11,8 +10,6 @@ / {
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
};
memory@0 {
@@ -43,7 +40,6 @@ &gmac0 {
phy-addr = <0xffffffff>; /* probe for phy addr */
max-frame-size = <3800>;
- status = "okay";
phy-handle = <&phy3>;
@@ -69,22 +65,8 @@ phy3: ethernet-phy@3 {
};
};
-&gpio0 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
&i2c1 {
- status = "okay";
isl12022: isl12022@6f {
- status = "okay";
compatible = "isil,isl12022";
reg = <0x6f>;
};
@@ -92,7 +74,6 @@ isl12022: isl12022@6f {
/* Following mappings are taken from arria10 socdk dts */
&mmc {
- status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
@@ -101,12 +82,3 @@ &mmc {
&osc1 {
clock-frequency = <33330000>;
};
-
-&uart1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "host";
-};
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Paweł Anikiel
@ 2022-06-03 9:23 ` Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts Paweł Anikiel
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel, Krzysztof Kozlowski
The ecc manager is a part of the Arria 10 SoC, move it to the correct
dts.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 10 ++++++++++
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 12 ------------
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 26bda2557fe8..4370e3cbbb4b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -736,6 +736,16 @@ emac0-tx-ecc@ff8c0c00 {
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index 4b21351f2694..b0d20101cd00 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -23,18 +23,6 @@ chosen {
};
};
-&eccmgr {
- sdmmca-ecc@ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
-
&gmac0 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts Paweł Anikiel
@ 2022-06-03 9:23 ` Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree Paweł Anikiel
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel, Krzysztof Kozlowski
Add atsha204a node to Mercury+ AA1 dts
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index b0d20101cd00..ad7cd14de6b6 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
#include "socfpga_arria10.dtsi"
@@ -54,6 +57,11 @@ phy3: ethernet-phy@3 {
};
&i2c1 {
+ atsha204a: crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
isl12022: isl12022@6f {
compatible = "isil,isl12022";
reg = <0x6f>;
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
` (2 preceding siblings ...)
2022-06-03 9:23 ` [PATCH v4 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts Paweł Anikiel
@ 2022-06-03 9:23 ` Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board Paweł Anikiel
2022-06-14 15:47 ` [PATCH v4 0/5] Add Chameleon v3 devicetree Dinh Nguyen
5 siblings, 0 replies; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel, Krzysztof Kozlowski
Add devicetree for the Google Chameleon v3 board.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 023c8b4ba45c..9417106d3289 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1146,6 +1146,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 000000000000..422d00cd4c74
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ssm2603: audio-codec@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ u80: gpio@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+&mmc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
` (3 preceding siblings ...)
2022-06-03 9:23 ` [PATCH v4 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree Paweł Anikiel
@ 2022-06-03 9:23 ` Paweł Anikiel
2022-06-03 10:18 ` Krzysztof Kozlowski
2022-06-14 15:47 ` [PATCH v4 0/5] Add Chameleon v3 devicetree Dinh Nguyen
5 siblings, 1 reply; 8+ messages in thread
From: Paweł Anikiel @ 2022-06-03 9:23 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream,
Paweł Anikiel
Add Mercury+ AA1 boards category, together with the Chameleon v3 board.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
---
Documentation/devicetree/bindings/arm/altera.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 5e2017c0a051..799ab0d2448b 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -25,7 +25,14 @@ properties:
items:
- enum:
- altr,socfpga-arria10-socdk
- - enclustra,mercury-aa1
+ - const: altr,socfpga-arria10
+ - const: altr,socfpga
+
+ - description: Mercury+ AA1 boards
+ items:
+ - enum:
+ - google,chameleon-v3
+ - const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
--
2.36.1.255.ge46751e96f-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board
2022-06-03 9:23 ` [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board Paweł Anikiel
@ 2022-06-03 10:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-03 10:18 UTC (permalink / raw)
To: Paweł Anikiel, robh+dt, krzysztof.kozlowski+dt, dinguyen
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream
On 03/06/2022 11:23, Paweł Anikiel wrote:
> Add Mercury+ AA1 boards category, together with the Chameleon v3 board.
>
> Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 0/5] Add Chameleon v3 devicetree
2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
` (4 preceding siblings ...)
2022-06-03 9:23 ` [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board Paweł Anikiel
@ 2022-06-14 15:47 ` Dinh Nguyen
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2022-06-14 15:47 UTC (permalink / raw)
To: Paweł Anikiel, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, amstan, upstream
On 6/3/22 04:23, Paweł Anikiel wrote:
> The Google Chameleon v3 is a board made for testing both video and audio
> interfaces of external devices. It acts as a base board for the
> Mercury+ AA1 module.
>
> socfpga_arria10_mercury_aa1.dtsi and socfpga_arria10_chameleonv3.dts
> have also been sent to u-boot:
> https://lists.denx.de/pipermail/u-boot/2022-May/485107.html
> https://lists.denx.de/pipermail/u-boot/2022-May/485111.html
>
> v4 changes:
> - remove enclustra,mercury-aa1 from Arria 10 boards in dt-bindings
>
> v3 changes:
> - make seperate group for Chameleon v3 in dt-bindings
> - add blank line after copyright header
>
> v2 changes:
> - split first patch into three
> - move sdmmc-ecc node to socfpga_arria10.dtsi (instead of removing it entirely)
> - use generic names for dts node names
> - keep the enclustra,mercury-aa1 compatible
>
> Paweł Anikiel (5):
> ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
> ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
> ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
> ARM: dts: socfpga: Add Google Chameleon v3 devicetree
> dt-bindings: altera: Add Chameleon v3 board
>
> .../devicetree/bindings/arm/altera.yaml | 9 +-
> arch/arm/boot/dts/Makefile | 2 +-
> arch/arm/boot/dts/socfpga_arria10.dtsi | 10 +++
> .../boot/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++
> ...1.dts => socfpga_arria10_mercury_aa1.dtsi} | 48 ++--------
> 5 files changed, 117 insertions(+), 42 deletions(-)
> create mode 100644 arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
> rename arch/arm/boot/dts/{socfpga_arria10_mercury_aa1.dts => socfpga_arria10_mercury_aa1.dtsi} (70%)
>
Whole series applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 8+ messages in thread
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2022-06-03 9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree Paweł Anikiel
2022-06-03 9:23 ` [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board Paweł Anikiel
2022-06-03 10:18 ` Krzysztof Kozlowski
2022-06-14 15:47 ` [PATCH v4 0/5] Add Chameleon v3 devicetree Dinh Nguyen
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