* [PATCH 0/2] Lattice ECP5 FPGA manager @ 2022-07-14 12:26 Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 1/2] fpga: ecp5-spi: add " Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov 0 siblings, 2 replies; 8+ messages in thread From: Ivan Bornyakov @ 2022-07-14 12:26 UTC (permalink / raw) To: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt Cc: Ivan Bornyakov, linux-fpga, devicetree, linux-kernel, system Add support to the FPGA manager for programming Lattice ECP5 FPGA over slave SPI interface with .bit formatted uncompressed bitstream image. Ivan Bornyakov (2): fpga: ecp5-spi: add Lattice ECP5 FPGA manager dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++ drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/ecp5-spi.c | 275 ++++++++++++++++++ 4 files changed, 354 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml create mode 100644 drivers/fpga/ecp5-spi.c -- 2.37.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] fpga: ecp5-spi: add Lattice ECP5 FPGA manager 2022-07-14 12:26 [PATCH 0/2] Lattice ECP5 FPGA manager Ivan Bornyakov @ 2022-07-14 12:26 ` Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov 1 sibling, 0 replies; 8+ messages in thread From: Ivan Bornyakov @ 2022-07-14 12:26 UTC (permalink / raw) To: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt Cc: Ivan Bornyakov, linux-fpga, devicetree, linux-kernel, system Add support to the FPGA manager for programming Lattice ECP5 FPGA over slave SPI interface with .bit formatted uncompressed bitstream image. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> --- drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/ecp5-spi.c | 275 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 283 insertions(+) create mode 100644 drivers/fpga/ecp5-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 6c416955da53..920277a08ed9 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -263,4 +263,11 @@ config FPGA_MGR_MICROCHIP_SPI programming over slave SPI interface with .dat formatted bitstream image. +config FPGA_MGR_ECP5_SPI + tristate "Lattice ECP5 SPI FPGA manager" + depends on SPI + help + FPGA manager driver support for Lattice ECP5 programming over slave + SPI interface with .bit formatted uncompressed bitstream image. + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 42ae8b58abce..17c7a3c4b385 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o +obj-$(CONFIG_FPGA_MGR_ECP5_SPI) += ecp5-spi.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/ecp5-spi.c b/drivers/fpga/ecp5-spi.c new file mode 100644 index 000000000000..29a18aaff3db --- /dev/null +++ b/drivers/fpga/ecp5-spi.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Lattice ECP5 FPGA programming over slave SPI interface. + */ + +#include <linux/delay.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/spi/spi.h> + +#define ECP5_SPI_MAX_SPEED_HZ 60000000 + +#define ECP5_SPI_ISC_ENABLE {0xC6, 0x00, 0x00, 0x00} +#define ECP5_SPI_ISC_DISABLE {0x26, 0x00, 0x00, 0x00} +#define ECP5_SPI_ISC_ERASE {0x0E, 0x01, 0x00, 0x00} +#define ECP5_SPI_LSC_INIT_ADDR {0x46, 0x00, 0x00, 0x00} +#define ECP5_SPI_LSC_BITSTREAM_BURST {0x7a, 0x00, 0x00, 0x00} +#define ECP5_SPI_LSC_CHECK_BUSY {0xF0, 0x00, 0x00, 0x00} + +#define ECP5_POLL_RETRIES 100000 + +struct ecp5_priv { + struct gpio_desc *program; + struct gpio_desc *init; + struct gpio_desc *done; + struct spi_device *spi; +}; + +static enum fpga_mgr_states ecp5_ops_state(struct fpga_manager *mgr) +{ + struct ecp5_priv *priv = mgr->priv; + + return gpiod_get_value(priv->done) ? FPGA_MGR_STATE_OPERATING : + FPGA_MGR_STATE_UNKNOWN; +} + +static int ecp5_poll_busy(struct spi_device *spi) +{ + const u8 lsc_check_busy[] = ECP5_SPI_LSC_CHECK_BUSY; + int ret, retries = ECP5_POLL_RETRIES; + struct spi_transfer xfers[2] = { 0 }; + u8 busy; + + xfers[0].tx_buf = lsc_check_busy; + xfers[0].len = sizeof(lsc_check_busy); + xfers[1].rx_buf = &busy; + xfers[1].len = sizeof(busy); + + while (retries--) { + ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers)); + if (ret) + return ret; + + if (!busy) + return 0; + + usleep_range(50, 100); + } + + return -EBUSY; +} + +static int ecp5_poll_gpio(struct gpio_desc *gpio, bool is_active) +{ + int value, retries = ECP5_POLL_RETRIES; + + while (retries--) { + value = gpiod_get_value(gpio); + if (value < 0) + return value; + + if ((!is_active && !value) || (is_active && value)) + return 0; + + ndelay(10); + } + + return -EFAULT; +} + +static int ecp5_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + const u8 lsc_bitstream_burst[] = ECP5_SPI_LSC_BITSTREAM_BURST; + const u8 lsc_init_addr[] = ECP5_SPI_LSC_INIT_ADDR; + const u8 isc_enable[] = ECP5_SPI_ISC_ENABLE; + const u8 isc_erase[] = ECP5_SPI_ISC_ERASE; + struct ecp5_priv *priv = mgr->priv; + struct spi_device *spi = priv->spi; + struct device *dev = &mgr->dev; + struct spi_transfer isc_xfers[] = { + { + .tx_buf = isc_enable, + .len = sizeof(isc_enable), + .cs_change = 1, + }, { + .tx_buf = isc_erase, + .len = sizeof(isc_erase), + }, + }; + struct spi_transfer lsc_xfers[] = { + { + .tx_buf = lsc_init_addr, + .len = sizeof(lsc_init_addr), + .cs_change = 1, + }, { + .tx_buf = lsc_bitstream_burst, + .len = sizeof(lsc_bitstream_burst), + .cs_change = 1, + }, + }; + int ret; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(dev, "Partial reconfiguration is not supported\n"); + return -EOPNOTSUPP; + } + + /* Enter init mode */ + gpiod_set_value(priv->program, 1); + + ret = ecp5_poll_gpio(priv->init, true); + if (!ret) + ret = ecp5_poll_gpio(priv->done, false); + + if (ret) { + dev_err(dev, "Failed to go to initialization mode\n"); + return ret; + } + + /* Enter program mode */ + gpiod_set_value(priv->program, 0); + + ret = ecp5_poll_gpio(priv->init, false); + if (ret) { + dev_err(dev, "Failed to go to program mode\n"); + return ret; + } + + /* Enter ISC mode */ + ret = spi_sync_transfer(spi, isc_xfers, ARRAY_SIZE(isc_xfers)); + if (!ret) + ret = ecp5_poll_busy(spi); + + if (ret) { + dev_err(dev, "Failed to go to ISC mode\n"); + return ret; + } + + /* Prepare for bitstream burst write */ + return spi_sync_transfer(spi, lsc_xfers, ARRAY_SIZE(lsc_xfers)); +} + +static int ecp5_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) +{ + struct ecp5_priv *priv = mgr->priv; + struct spi_transfer xfer = { + .tx_buf = buf, + .len = count, + .cs_change = 1, + }; + + return spi_sync_transfer(priv->spi, &xfer, 1); +} + +static int ecp5_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + const u8 isc_disable[] = ECP5_SPI_ISC_DISABLE; + struct ecp5_priv *priv = mgr->priv; + struct spi_device *spi = priv->spi; + struct device *dev = &mgr->dev; + int ret; + + /* Toggle CS and wait for bitstream write to finish */ + ret = spi_write(spi, NULL, 0); + if (!ret) + ret = ecp5_poll_busy(spi); + + if (ret) { + dev_err(dev, "Error while waiting bitstream write to finish\n"); + return ret; + } + + /* Exit ISC mode */ + ret = spi_write(spi, isc_disable, sizeof(isc_disable)); + if (!ret) + ret = ecp5_poll_gpio(priv->done, true); + + if (ret) + dev_err(dev, "Failed to finish ISC\n"); + + return ret; +} + +static const struct fpga_manager_ops ecp5_fpga_ops = { + .state = ecp5_ops_state, + .write_init = ecp5_ops_write_init, + .write = ecp5_ops_write, + .write_complete = ecp5_ops_write_complete, +}; + +static int ecp5_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct fpga_manager *mgr; + struct ecp5_priv *priv; + int ret; + + if (spi->max_speed_hz > ECP5_SPI_MAX_SPEED_HZ) { + dev_err(dev, "SPI speed %u is too high, maximum speed is %u\n", + spi->max_speed_hz, ECP5_SPI_MAX_SPEED_HZ); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->spi = spi; + + priv->done = devm_gpiod_get(dev, "done", GPIOD_IN); + if (IS_ERR(priv->done)) { + ret = PTR_ERR(priv->done); + dev_err(dev, "Failed to get DONE GPIO: %d\n", ret); + return ret; + } + + priv->init = devm_gpiod_get(dev, "init", GPIOD_IN); + if (IS_ERR(priv->init)) { + ret = PTR_ERR(priv->init); + dev_err(dev, "Failed to get INIT GPIO: %d\n", ret); + return ret; + } + + priv->program = devm_gpiod_get(dev, "program", GPIOD_OUT_LOW); + if (IS_ERR(priv->program)) { + ret = PTR_ERR(priv->program); + dev_err(dev, "Failed to get PROGRAM GPIO: %d\n", ret); + return ret; + } + + mgr = devm_fpga_mgr_register(dev, "Lattice ECP5 SPI FPGA Manager", + &ecp5_fpga_ops, priv); + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct spi_device_id ecp5_spi_ids[] = { + { .name = "ecp5-spi-fpga-mgr" }, + {}, +}; +MODULE_DEVICE_TABLE(spi, ecp5_spi_ids); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id ecp5_of_ids[] = { + { .compatible = "lattice,ecp5-spi-fpga-mgr" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ecp5_of_ids); +#endif /* IS_ENABLED(CONFIG_OF) */ + +static struct spi_driver ecp5_driver = { + .probe = ecp5_probe, + .id_table = ecp5_spi_ids, + .driver = { + .name = "lattice_ecp5_spi_fpga_mgr", + .of_match_table = of_match_ptr(ecp5_of_ids), + }, +}; + +module_spi_driver(ecp5_driver); + +MODULE_DESCRIPTION("Lattice ECP5 SPI FPGA Manager"); +MODULE_LICENSE("GPL"); -- 2.37.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-14 12:26 [PATCH 0/2] Lattice ECP5 FPGA manager Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 1/2] fpga: ecp5-spi: add " Ivan Bornyakov @ 2022-07-14 12:26 ` Ivan Bornyakov 2022-07-15 9:33 ` Krzysztof Kozlowski 1 sibling, 1 reply; 8+ messages in thread From: Ivan Bornyakov @ 2022-07-14 12:26 UTC (permalink / raw) To: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt Cc: Ivan Bornyakov, linux-fpga, devicetree, linux-kernel, system Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave SPI to load .bit formatted uncompressed bitstream image. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> --- .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml new file mode 100644 index 000000000000..79868f9c84e2 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lattice ECP5 FPGA manager. + +maintainers: + - Ivan Bornyakov <i.bornyakov@metrotek.ru> + +description: + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to + load the uncompressed bitstream in .bit format. + +properties: + compatible: + enum: + - lattice,ecp5-spi-fpga-mgr + + reg: + description: SPI chip select + maxItems: 1 + + spi-max-frequency: + maximum: 60000000 + + program-gpios: + description: + A GPIO line connected to PROGRAMN (active low) pin of the device. + Initiates configuration sequence. + maxItems: 1 + + init-gpios: + description: + A GPIO line connected to INITN (active low) pin of the device. + Indicates the FPGA is ready to be configured. + maxItems: 1 + + done-gpios: + description: + A GPIO line connected to DONE (active high) pin of the device. + Indicates that the configuration sequence is complete. + maxItems: 1 + +required: + - compatible + - reg + - program-gpios + - init-gpios + - done-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga_mgr@0 { + compatible = "lattice,ecp5-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + program-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + init-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + }; + }; -- 2.37.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-14 12:26 ` [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov @ 2022-07-15 9:33 ` Krzysztof Kozlowski 2022-07-15 10:03 ` Ivan Bornyakov 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-07-15 9:33 UTC (permalink / raw) To: Ivan Bornyakov, mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt Cc: linux-fpga, devicetree, linux-kernel, system On 14/07/2022 14:26, Ivan Bornyakov wrote: > Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave > SPI to load .bit formatted uncompressed bitstream image. > > Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> > --- > .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > > diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > new file mode 100644 > index 000000000000..79868f9c84e2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Lattice ECP5 FPGA manager. > + > +maintainers: > + - Ivan Bornyakov <i.bornyakov@metrotek.ru> > + > +description: > + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to > + load the uncompressed bitstream in .bit format. s/Device Tree Bindings for// Instead describe the hardware you are adding bindings for. What is a "Manager"? It is so broad and unspecific... It is some dedicated hardware to communicate with FPGA or you just called this regular FPGA interface exposed to the CPU/SoC? > + > +properties: > + compatible: > + enum: > + - lattice,ecp5-spi-fpga-mgr Do not encode interface name in compatible so no "spi". > + > + reg: > + description: SPI chip select > + maxItems: 1 > + > + spi-max-frequency: > + maximum: 60000000 Reference spi/spi-peripheral-props.yaml in allOf > + > + program-gpios: > + description: > + A GPIO line connected to PROGRAMN (active low) pin of the device. > + Initiates configuration sequence. > + maxItems: 1 > + > + init-gpios: > + description: > + A GPIO line connected to INITN (active low) pin of the device. > + Indicates the FPGA is ready to be configured. > + maxItems: 1 > + > + done-gpios: > + description: > + A GPIO line connected to DONE (active high) pin of the device. > + Indicates that the configuration sequence is complete. > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - program-gpios > + - init-gpios > + - done-gpios > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/gpio/gpio.h> > + > + spi { > + #address-cells = <1>; Wrong indentation. 4-spaces for DTS example. > + #size-cells = <0>; > + > + fpga_mgr@0 { No underscores in node names. > + compatible = "lattice,ecp5-spi-fpga-mgr"; > + spi-max-frequency = <20000000>; > + reg = <0>; > + program-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > + init-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; > + done-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; > + }; > + }; Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-15 9:33 ` Krzysztof Kozlowski @ 2022-07-15 10:03 ` Ivan Bornyakov 2022-07-18 13:06 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: Ivan Bornyakov @ 2022-07-15 10:03 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt, linux-fpga, devicetree, linux-kernel, system On Fri, Jul 15, 2022 at 11:33:54AM +0200, Krzysztof Kozlowski wrote: > On 14/07/2022 14:26, Ivan Bornyakov wrote: > > Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave > > SPI to load .bit formatted uncompressed bitstream image. > > > > Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> > > --- > > .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ > > 1 file changed, 71 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > > > > diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > > new file mode 100644 > > index 000000000000..79868f9c84e2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > > @@ -0,0 +1,71 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Lattice ECP5 FPGA manager. > > + > > +maintainers: > > + - Ivan Bornyakov <i.bornyakov@metrotek.ru> > > + > > +description: > > + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to > > + load the uncompressed bitstream in .bit format. > > s/Device Tree Bindings for// > > Instead describe the hardware you are adding bindings for. What is a > "Manager"? It is so broad and unspecific... It is some dedicated > hardware to communicate with FPGA or you just called this regular FPGA > interface exposed to the CPU/SoC? > "FPGA Manager" is a kernel subsystem that exports a set of functions for programming an FPGA with a bitstream image. See Documentation/driver-api/fpga/fpga-mgr.rst > > + > > +properties: > > + compatible: > > + enum: > > + - lattice,ecp5-spi-fpga-mgr > > Do not encode interface name in compatible so no "spi". > Recently when I submitted FPGA manager for Microchip PolarFire, I was asked the opposite, to add "spi" in compatible. The reason was that FPGA can be programmed through other interfaces as well. > > + > > + reg: > > + description: SPI chip select > > + maxItems: 1 > > + > > + spi-max-frequency: > > + maximum: 60000000 > > Reference spi/spi-peripheral-props.yaml in allOf > > > + > > + program-gpios: > > + description: > > + A GPIO line connected to PROGRAMN (active low) pin of the device. > > + Initiates configuration sequence. > > + maxItems: 1 > > + > > + init-gpios: > > + description: > > + A GPIO line connected to INITN (active low) pin of the device. > > + Indicates the FPGA is ready to be configured. > > + maxItems: 1 > > + > > + done-gpios: > > + description: > > + A GPIO line connected to DONE (active high) pin of the device. > > + Indicates that the configuration sequence is complete. > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - program-gpios > > + - init-gpios > > + - done-gpios > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/gpio/gpio.h> > > + > > + spi { > > + #address-cells = <1>; > > Wrong indentation. 4-spaces for DTS example. > > > + #size-cells = <0>; > > + > > + fpga_mgr@0 { > > No underscores in node names. > > > + compatible = "lattice,ecp5-spi-fpga-mgr"; > > + spi-max-frequency = <20000000>; > > + reg = <0>; > > + program-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > > + init-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; > > + done-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; > > + }; > > + }; > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-15 10:03 ` Ivan Bornyakov @ 2022-07-18 13:06 ` Krzysztof Kozlowski 2022-07-18 13:46 ` Ivan Bornyakov 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-07-18 13:06 UTC (permalink / raw) To: Ivan Bornyakov Cc: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt, linux-fpga, devicetree, linux-kernel, system On 15/07/2022 12:03, Ivan Bornyakov wrote: > On Fri, Jul 15, 2022 at 11:33:54AM +0200, Krzysztof Kozlowski wrote: >> On 14/07/2022 14:26, Ivan Bornyakov wrote: >>> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave >>> SPI to load .bit formatted uncompressed bitstream image. >>> >>> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> >>> --- >>> .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ >>> 1 file changed, 71 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>> new file mode 100644 >>> index 000000000000..79868f9c84e2 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>> @@ -0,0 +1,71 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Lattice ECP5 FPGA manager. >>> + >>> +maintainers: >>> + - Ivan Bornyakov <i.bornyakov@metrotek.ru> >>> + >>> +description: >>> + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to >>> + load the uncompressed bitstream in .bit format. >> >> s/Device Tree Bindings for// >> >> Instead describe the hardware you are adding bindings for. What is a >> "Manager"? It is so broad and unspecific... It is some dedicated >> hardware to communicate with FPGA or you just called this regular FPGA >> interface exposed to the CPU/SoC? >> > > "FPGA Manager" is a kernel subsystem that exports a set of functions for > programming an FPGA with a bitstream image. > See Documentation/driver-api/fpga/fpga-mgr.rst This is what you want to include in the bindings document? How is it related to bindings? We do not talk about driver API but we talk about hardware. Bindings are for the hardware. > >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - lattice,ecp5-spi-fpga-mgr >> >> Do not encode interface name in compatible so no "spi". >> > > Recently when I submitted FPGA manager for Microchip PolarFire, I was > asked the opposite, to add "spi" in compatible. The reason was that FPGA > can be programmed through other interfaces as well. I don't see such comment from Rob (DT maintainer): https://lore.kernel.org/all/?q=%22dt-bindings%3A+fpga%3A+add+binding+doc+for+microchip-spi+fpga+mgr%22 Can you point me to it? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-18 13:06 ` Krzysztof Kozlowski @ 2022-07-18 13:46 ` Ivan Bornyakov 2022-07-18 14:41 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: Ivan Bornyakov @ 2022-07-18 13:46 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt, linux-fpga, devicetree, linux-kernel, system On Mon, Jul 18, 2022 at 03:06:18PM +0200, Krzysztof Kozlowski wrote: > On 15/07/2022 12:03, Ivan Bornyakov wrote: > > On Fri, Jul 15, 2022 at 11:33:54AM +0200, Krzysztof Kozlowski wrote: > >> On 14/07/2022 14:26, Ivan Bornyakov wrote: > >>> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave > >>> SPI to load .bit formatted uncompressed bitstream image. > >>> > >>> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> > >>> --- > >>> .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ > >>> 1 file changed, 71 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > >>> new file mode 100644 > >>> index 000000000000..79868f9c84e2 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml > >>> @@ -0,0 +1,71 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: Lattice ECP5 FPGA manager. > >>> + > >>> +maintainers: > >>> + - Ivan Bornyakov <i.bornyakov@metrotek.ru> > >>> + > >>> +description: > >>> + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to > >>> + load the uncompressed bitstream in .bit format. > >> > >> s/Device Tree Bindings for// > >> > >> Instead describe the hardware you are adding bindings for. What is a > >> "Manager"? It is so broad and unspecific... It is some dedicated > >> hardware to communicate with FPGA or you just called this regular FPGA > >> interface exposed to the CPU/SoC? > >> > > > > "FPGA Manager" is a kernel subsystem that exports a set of functions for > > programming an FPGA with a bitstream image. > > See Documentation/driver-api/fpga/fpga-mgr.rst > > This is what you want to include in the bindings document? How is it > related to bindings? We do not talk about driver API but we talk about > hardware. Bindings are for the hardware. > I've send out v3 not too long ago. If you found the wording there not good enough, could you look through Documentation/devicetree/bindings/fpga/ and point me to a proper example? > > > >>> + > >>> +properties: > >>> + compatible: > >>> + enum: > >>> + - lattice,ecp5-spi-fpga-mgr > >> > >> Do not encode interface name in compatible so no "spi". > >> > > > > Recently when I submitted FPGA manager for Microchip PolarFire, I was > > asked the opposite, to add "spi" in compatible. The reason was that FPGA > > can be programmed through other interfaces as well. > > I don't see such comment from Rob (DT maintainer): > https://lore.kernel.org/all/?q=%22dt-bindings%3A+fpga%3A+add+binding+doc+for+microchip-spi+fpga+mgr%22 > > Can you point me to it? > Yeah, it was not Rob but other developer: https://lore.kernel.org/all/79328410-e56f-7c8a-9d17-de9bfdb98f51@microchip.com/ And at that point I had not even written the bindings doc, so neither you nor Rob weren't in the Cc. But eventually Rob reviewed DT bindings doc for PolarFire with compatible string to be "microchip,mpf-spi-fpga-mgr" https://lore.kernel.org/all/YkORrgC1FdzaKCMW@robh.at.kernel.org/ So I thought it was OK. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr 2022-07-18 13:46 ` Ivan Bornyakov @ 2022-07-18 14:41 ` Krzysztof Kozlowski 0 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-07-18 14:41 UTC (permalink / raw) To: Ivan Bornyakov Cc: mdf, hao.wu, yilun.xu, trix, robh+dt, krzysztof.kozlowski+dt, linux-fpga, devicetree, linux-kernel, system On 18/07/2022 15:46, Ivan Bornyakov wrote: > On Mon, Jul 18, 2022 at 03:06:18PM +0200, Krzysztof Kozlowski wrote: >> On 15/07/2022 12:03, Ivan Bornyakov wrote: >>> On Fri, Jul 15, 2022 at 11:33:54AM +0200, Krzysztof Kozlowski wrote: >>>> On 14/07/2022 14:26, Ivan Bornyakov wrote: >>>>> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave >>>>> SPI to load .bit formatted uncompressed bitstream image. >>>>> >>>>> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> >>>>> --- >>>>> .../fpga/lattice,ecp5-spi-fpga-mgr.yaml | 71 +++++++++++++++++++ >>>>> 1 file changed, 71 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>>>> new file mode 100644 >>>>> index 000000000000..79868f9c84e2 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-spi-fpga-mgr.yaml >>>>> @@ -0,0 +1,71 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-spi-fpga-mgr.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: Lattice ECP5 FPGA manager. >>>>> + >>>>> +maintainers: >>>>> + - Ivan Bornyakov <i.bornyakov@metrotek.ru> >>>>> + >>>>> +description: >>>>> + Device Tree Bindings for Lattice ECP5 FPGA Manager using slave SPI to >>>>> + load the uncompressed bitstream in .bit format. >>>> >>>> s/Device Tree Bindings for// >>>> >>>> Instead describe the hardware you are adding bindings for. What is a >>>> "Manager"? It is so broad and unspecific... It is some dedicated >>>> hardware to communicate with FPGA or you just called this regular FPGA >>>> interface exposed to the CPU/SoC? >>>> >>> >>> "FPGA Manager" is a kernel subsystem that exports a set of functions for >>> programming an FPGA with a bitstream image. >>> See Documentation/driver-api/fpga/fpga-mgr.rst >> >> This is what you want to include in the bindings document? How is it >> related to bindings? We do not talk about driver API but we talk about >> hardware. Bindings are for the hardware. >> > > I've send out v3 not too long ago. If you found the wording there not > good enough, could you look through > Documentation/devicetree/bindings/fpga/ and point me to a proper example? > >>> >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + enum: >>>>> + - lattice,ecp5-spi-fpga-mgr >>>> >>>> Do not encode interface name in compatible so no "spi". >>>> >>> >>> Recently when I submitted FPGA manager for Microchip PolarFire, I was >>> asked the opposite, to add "spi" in compatible. The reason was that FPGA >>> can be programmed through other interfaces as well. >> >> I don't see such comment from Rob (DT maintainer): >> https://lore.kernel.org/all/?q=%22dt-bindings%3A+fpga%3A+add+binding+doc+for+microchip-spi+fpga+mgr%22 >> >> Can you point me to it? >> > > Yeah, it was not Rob but other developer: > https://lore.kernel.org/all/79328410-e56f-7c8a-9d17-de9bfdb98f51@microchip.com/ > The type of bus should not be included in the compatible. It's obvious by looking at the parent, so Conor's comment was not helpful, IMO. > And at that point I had not even written the bindings doc, so neither > you nor Rob weren't in the Cc. > > But eventually Rob reviewed DT bindings doc for PolarFire with > compatible string to be "microchip,mpf-spi-fpga-mgr" > https://lore.kernel.org/all/YkORrgC1FdzaKCMW@robh.at.kernel.org/ > > So I thought it was OK. If spi was at the end, probably would be easier to spot thus would trigger a comment. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-07-18 14:41 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-07-14 12:26 [PATCH 0/2] Lattice ECP5 FPGA manager Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 1/2] fpga: ecp5-spi: add " Ivan Bornyakov 2022-07-14 12:26 ` [PATCH 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov 2022-07-15 9:33 ` Krzysztof Kozlowski 2022-07-15 10:03 ` Ivan Bornyakov 2022-07-18 13:06 ` Krzysztof Kozlowski 2022-07-18 13:46 ` Ivan Bornyakov 2022-07-18 14:41 ` Krzysztof Kozlowski
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).