* [PATCH] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
@ 2022-07-14 18:26 kan.liang
2022-07-20 13:57 ` Peter Zijlstra
2022-07-21 8:37 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
0 siblings, 2 replies; 3+ messages in thread
From: kan.liang @ 2022-07-14 18:26 UTC (permalink / raw)
To: peterz, mingo, acme, vincent.weaver, linux-kernel
Cc: mark.rutland, alexander.shishkin, jolsa, namhyung,
pawan.kumar.gupta, Kan Liang, stable
From: Kan Liang <kan.liang@linux.intel.com>
The fuzzer triggers the below trace.
[ 7763.384369] unchecked MSR access error: WRMSR to 0x689
(tried to write 0x1fffffff8101349e) at rIP: 0xffffffff810704a4
(native_write_msr+0x4/0x20)
[ 7763.397420] Call Trace:
[ 7763.399881] <TASK>
[ 7763.401994] intel_pmu_lbr_restore+0x9a/0x1f0
[ 7763.406363] intel_pmu_lbr_sched_task+0x91/0x1c0
[ 7763.410992] __perf_event_task_sched_in+0x1cd/0x240
On a machine with the LBR format LBR_FORMAT_EIP_FLAGS2, when the TSX is
disabled, a TSX quirk is required to access LBR from registers.
The lbr_from_signext_quirk_needed() is introduced to determine whether
the TSX quirk should be applied. However, the
lbr_from_signext_quirk_needed() is invoked before the
intel_pmu_lbr_init(), which parses the LBR format information. Without
the correct LBR format information, the TSX quirk never be applied.
Move the lbr_from_signext_quirk_needed() into the intel_pmu_lbr_init().
Checking x86_pmu.lbr_has_tsx in the lbr_from_signext_quirk_needed() is
not required anymore.
Both LBR_FORMAT_EIP_FLAGS2 and LBR_FORMAT_INFO have LBR_TSX flag, but
only the LBR_FORMAT_EIP_FLAGS2 requirs the quirk. Update the comments
accordingly.
Fixes: 1ac7fd8159a8 ("perf/x86/intel/lbr: Support LBR format V7")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/x86/events/intel/lbr.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 13179f31fe10..4f70fb6c2c1e 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -278,9 +278,9 @@ enum {
};
/*
- * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
- * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
- * TSX is not supported they have no consistent behavior:
+ * For format LBR_FORMAT_EIP_FLAGS2, bits 61:62 in MSR_LAST_BRANCH_FROM_x
+ * are the TSX flags when TSX is supported, but when TSX is not supported
+ * they have no consistent behavior:
*
* - For wrmsr(), bits 61:62 are considered part of the sign extension.
* - For HW updates (branch captures) bits 61:62 are always OFF and are not
@@ -288,7 +288,7 @@ enum {
*
* Therefore, if:
*
- * 1) LBR has TSX format
+ * 1) LBR format LBR_FORMAT_EIP_FLAGS2
* 2) CPU has no TSX support enabled
*
* ... then any value passed to wrmsr() must be sign extended to 63 bits and any
@@ -300,7 +300,7 @@ static inline bool lbr_from_signext_quirk_needed(void)
bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
boot_cpu_has(X86_FEATURE_RTM);
- return !tsx_support && x86_pmu.lbr_has_tsx;
+ return !tsx_support;
}
static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
@@ -1609,9 +1609,6 @@ void intel_pmu_lbr_init_hsw(void)
x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0);
-
- if (lbr_from_signext_quirk_needed())
- static_branch_enable(&lbr_from_quirk_key);
}
/* skylake */
@@ -1702,7 +1699,11 @@ void intel_pmu_lbr_init(void)
switch (x86_pmu.intel_cap.lbr_format) {
case LBR_FORMAT_EIP_FLAGS2:
x86_pmu.lbr_has_tsx = 1;
- fallthrough;
+ x86_pmu.lbr_from_flags = 1;
+ if (lbr_from_signext_quirk_needed())
+ static_branch_enable(&lbr_from_quirk_key);
+ break;
+
case LBR_FORMAT_EIP_FLAGS:
x86_pmu.lbr_from_flags = 1;
break;
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
2022-07-14 18:26 [PATCH] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW kan.liang
@ 2022-07-20 13:57 ` Peter Zijlstra
2022-07-21 8:37 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
1 sibling, 0 replies; 3+ messages in thread
From: Peter Zijlstra @ 2022-07-20 13:57 UTC (permalink / raw)
To: kan.liang
Cc: mingo, acme, vincent.weaver, linux-kernel, mark.rutland,
alexander.shishkin, jolsa, namhyung, pawan.kumar.gupta, stable
On Thu, Jul 14, 2022 at 11:26:30AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The fuzzer triggers the below trace.
>
> [ 7763.384369] unchecked MSR access error: WRMSR to 0x689
> (tried to write 0x1fffffff8101349e) at rIP: 0xffffffff810704a4
> (native_write_msr+0x4/0x20)
> [ 7763.397420] Call Trace:
> [ 7763.399881] <TASK>
> [ 7763.401994] intel_pmu_lbr_restore+0x9a/0x1f0
> [ 7763.406363] intel_pmu_lbr_sched_task+0x91/0x1c0
> [ 7763.410992] __perf_event_task_sched_in+0x1cd/0x240
>
> On a machine with the LBR format LBR_FORMAT_EIP_FLAGS2, when the TSX is
> disabled, a TSX quirk is required to access LBR from registers.
> The lbr_from_signext_quirk_needed() is introduced to determine whether
> the TSX quirk should be applied. However, the
> lbr_from_signext_quirk_needed() is invoked before the
> intel_pmu_lbr_init(), which parses the LBR format information. Without
> the correct LBR format information, the TSX quirk never be applied.
>
> Move the lbr_from_signext_quirk_needed() into the intel_pmu_lbr_init().
> Checking x86_pmu.lbr_has_tsx in the lbr_from_signext_quirk_needed() is
> not required anymore.
>
> Both LBR_FORMAT_EIP_FLAGS2 and LBR_FORMAT_INFO have LBR_TSX flag, but
> only the LBR_FORMAT_EIP_FLAGS2 requirs the quirk. Update the comments
> accordingly.
>
> Fixes: 1ac7fd8159a8 ("perf/x86/intel/lbr: Support LBR format V7")
> Reported-by: Vince Weaver <vincent.weaver@maine.edu>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread
* [tip: perf/urgent] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
2022-07-14 18:26 [PATCH] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW kan.liang
2022-07-20 13:57 ` Peter Zijlstra
@ 2022-07-21 8:37 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot2 for Kan Liang @ 2022-07-21 8:37 UTC (permalink / raw)
To: linux-tip-commits
Cc: Vince Weaver, Kan Liang, Peter Zijlstra (Intel),
stable, x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: b0380e13502adf7dd8be4c47d622c3522aae6c63
Gitweb: https://git.kernel.org/tip/b0380e13502adf7dd8be4c47d622c3522aae6c63
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Thu, 14 Jul 2022 11:26:30 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 20 Jul 2022 19:24:55 +02:00
perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
The fuzzer triggers the below trace.
[ 7763.384369] unchecked MSR access error: WRMSR to 0x689
(tried to write 0x1fffffff8101349e) at rIP: 0xffffffff810704a4
(native_write_msr+0x4/0x20)
[ 7763.397420] Call Trace:
[ 7763.399881] <TASK>
[ 7763.401994] intel_pmu_lbr_restore+0x9a/0x1f0
[ 7763.406363] intel_pmu_lbr_sched_task+0x91/0x1c0
[ 7763.410992] __perf_event_task_sched_in+0x1cd/0x240
On a machine with the LBR format LBR_FORMAT_EIP_FLAGS2, when the TSX is
disabled, a TSX quirk is required to access LBR from registers.
The lbr_from_signext_quirk_needed() is introduced to determine whether
the TSX quirk should be applied. However, the
lbr_from_signext_quirk_needed() is invoked before the
intel_pmu_lbr_init(), which parses the LBR format information. Without
the correct LBR format information, the TSX quirk never be applied.
Move the lbr_from_signext_quirk_needed() into the intel_pmu_lbr_init().
Checking x86_pmu.lbr_has_tsx in the lbr_from_signext_quirk_needed() is
not required anymore.
Both LBR_FORMAT_EIP_FLAGS2 and LBR_FORMAT_INFO have LBR_TSX flag, but
only the LBR_FORMAT_EIP_FLAGS2 requirs the quirk. Update the comments
accordingly.
Fixes: 1ac7fd8159a8 ("perf/x86/intel/lbr: Support LBR format V7")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20220714182630.342107-1-kan.liang@linux.intel.com
---
arch/x86/events/intel/lbr.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 13179f3..4f70fb6 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -278,9 +278,9 @@ enum {
};
/*
- * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
- * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
- * TSX is not supported they have no consistent behavior:
+ * For format LBR_FORMAT_EIP_FLAGS2, bits 61:62 in MSR_LAST_BRANCH_FROM_x
+ * are the TSX flags when TSX is supported, but when TSX is not supported
+ * they have no consistent behavior:
*
* - For wrmsr(), bits 61:62 are considered part of the sign extension.
* - For HW updates (branch captures) bits 61:62 are always OFF and are not
@@ -288,7 +288,7 @@ enum {
*
* Therefore, if:
*
- * 1) LBR has TSX format
+ * 1) LBR format LBR_FORMAT_EIP_FLAGS2
* 2) CPU has no TSX support enabled
*
* ... then any value passed to wrmsr() must be sign extended to 63 bits and any
@@ -300,7 +300,7 @@ static inline bool lbr_from_signext_quirk_needed(void)
bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
boot_cpu_has(X86_FEATURE_RTM);
- return !tsx_support && x86_pmu.lbr_has_tsx;
+ return !tsx_support;
}
static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
@@ -1609,9 +1609,6 @@ void intel_pmu_lbr_init_hsw(void)
x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0);
-
- if (lbr_from_signext_quirk_needed())
- static_branch_enable(&lbr_from_quirk_key);
}
/* skylake */
@@ -1702,7 +1699,11 @@ void intel_pmu_lbr_init(void)
switch (x86_pmu.intel_cap.lbr_format) {
case LBR_FORMAT_EIP_FLAGS2:
x86_pmu.lbr_has_tsx = 1;
- fallthrough;
+ x86_pmu.lbr_from_flags = 1;
+ if (lbr_from_signext_quirk_needed())
+ static_branch_enable(&lbr_from_quirk_key);
+ break;
+
case LBR_FORMAT_EIP_FLAGS:
x86_pmu.lbr_from_flags = 1;
break;
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2022-07-14 18:26 [PATCH] perf/x86/intel/lbr: Fix unchecked MSR access error on HSW kan.liang
2022-07-20 13:57 ` Peter Zijlstra
2022-07-21 8:37 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
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