From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v7 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations
Date: Wed, 20 Jul 2022 20:53:42 +0530 [thread overview]
Message-ID: <20220720152348.2889109-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220720152348.2889109-1-apatel@ventanamicro.com>
The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/kernel/sbi.c | 8 +++++++-
arch/riscv/kernel/smp.c | 2 --
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..fc614650a2e3 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -643,8 +643,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
sbi_send_ipi(target);
}
+static void sbi_ipi_clear(void)
+{
+ csr_clear(CSR_IP, IE_SIE);
+}
+
static const struct riscv_ipi_ops sbi_ipi_ops = {
- .ipi_inject = sbi_send_cpumask_ipi
+ .ipi_inject = sbi_send_cpumask_ipi,
+ .ipi_clear = sbi_ipi_clear
};
void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index b5d30ea92292..6fd8b3cbec1b 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -89,8 +89,6 @@ void riscv_clear_ipi(void)
{
if (ipi_ops && ipi_ops->ipi_clear)
ipi_ops->ipi_clear();
-
- csr_clear(CSR_IP, IE_SIE);
}
EXPORT_SYMBOL_GPL(riscv_clear_ipi);
--
2.34.1
next prev parent reply other threads:[~2022-07-20 15:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-20 15:23 [PATCH v7 0/7] RISC-V IPI Improvements Anup Patel
2022-07-20 15:23 ` Anup Patel [this message]
2022-07-20 15:23 ` [PATCH v7 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Anup Patel
2022-07-20 15:23 ` [PATCH v7 3/7] genirq: Add mechanism to multiplex a single HW IPI Anup Patel
2022-07-21 11:00 ` Marc Zyngier
2022-07-21 11:44 ` Anup Patel
2022-07-21 12:09 ` Marc Zyngier
2022-07-21 12:26 ` Anup Patel
2022-07-20 15:23 ` [PATCH v7 4/7] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2022-07-20 15:23 ` [PATCH v7 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2022-07-20 15:23 ` [PATCH v7 6/7] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2022-07-20 15:23 ` [PATCH v7 7/7] RISC-V: Use IPIs for remote icache " Anup Patel
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