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From: Tomas Winkler <tomas.winkler@intel.com>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Tomas Winkler <tomas.winkler@intel.com>,
	Alexander Usyskin <alexander.usyskin@intel.com>,
	Vitaly Lubart <vitaly.lubart@intel.com>
Subject: [PATCH v6 04/14] drm/i915/gsc: add GSC XeHP SDV platform definition
Date: Sun, 24 Jul 2022 11:24:18 +0300	[thread overview]
Message-ID: <20220724082428.218628-5-tomas.winkler@intel.com> (raw)
In-Reply-To: <20220724082428.218628-1-tomas.winkler@intel.com>

From: Alexander Usyskin <alexander.usyskin@intel.com>

Define GSC on XeHP SDV (Intel(R) dGPU without display)

XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.

Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index f963c220bbff..bfc307e49bf9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
 	}
 };
 
+static const struct gsc_def gsc_def_xehpsdv[] = {
+	{
+		/* HECI1 not enabled on the device. */
+	},
+	{
+		.name = "mei-gscfi",
+		.bar = DG1_GSC_HECI2_BASE,
+		.bar_size = GSC_BAR_LENGTH,
+		.use_polling = true,
+		.slow_fw = true,
+	}
+};
+
 static const struct gsc_def gsc_def_dg2[] = {
 	{
 		.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
 
 	if (IS_DG1(i915)) {
 		def = &gsc_def_dg1[intf_id];
+	} else if (IS_XEHPSDV(i915)) {
+		def = &gsc_def_xehpsdv[intf_id];
 	} else if (IS_DG2(i915)) {
 		def = &gsc_def_dg2[intf_id];
 	} else {
-- 
2.35.3


  parent reply	other threads:[~2022-07-24  8:25 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-24  8:24 [PATCH v6 00/14] GSC support for XeHP SDV and DG2 Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 01/14] drm/i915/gsc: skip irq initialization if using polling Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 02/14] mei: add slow_fw flag to the mei auxiliary device Tomas Winkler
2022-07-24 13:44   ` Greg Kroah-Hartman
2022-07-24  8:24 ` [PATCH v6 03/14] drm/i915/gsc: add slow_fw flag to the gsc device definition Tomas Winkler
2022-07-24  8:24 ` Tomas Winkler [this message]
2022-07-24  8:24 ` [PATCH v6 05/14] mei: gsc: use polling instead of interrupts Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 06/14] mei: gsc: wait for reset thread on stop Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 07/14] mei: extend timeouts on slow devices Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 08/14] mei: bus: export common mkhi definitions into a separate header Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 09/14] mei: mkhi: add memory ready command Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 10/14] mei: gsc: setup gsc extended operational memory Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 11/14] mei: gsc: add transition to PXP mode in resume flow Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 12/14] mei: debugfs: add pxp mode to devstate in debugfs Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 13/14] drm/i915/gsc: allocate extended operational memory in LMEM Tomas Winkler
2022-07-24  8:24 ` [PATCH v6 14/14] HAX: drm/i915: force INTEL_MEI_GSC on for CI Tomas Winkler
2022-07-24 13:44 ` [PATCH v6 00/14] GSC support for XeHP SDV and DG2 Greg Kroah-Hartman

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