From: Samuel Holland <samuel@sholland.org>
To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev
Subject: [PATCH 2/4] nvmem: sunxi_sid: Drop the workaround on A64
Date: Sun, 14 Aug 2022 12:36:53 -0500 [thread overview]
Message-ID: <20220814173656.11856-3-samuel@sholland.org> (raw)
In-Reply-To: <20220814173656.11856-1-samuel@sholland.org>
Now that the SRAM readout code is fixed by using 32-bit accesses, it
always returns the same values as register readout, so the A64 variant
no longer needs the workaround. This makes the D1 variant structure
redundant, so remove it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/nvmem/sunxi_sid.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index 92dfe4cb10e3..a970f1741cc6 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -197,15 +197,9 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg = {
.need_register_readout = true,
};
-static const struct sunxi_sid_cfg sun20i_d1_cfg = {
- .value_offset = 0x200,
- .size = 0x100,
-};
-
static const struct sunxi_sid_cfg sun50i_a64_cfg = {
.value_offset = 0x200,
.size = 0x100,
- .need_register_readout = true,
};
static const struct sunxi_sid_cfg sun50i_h6_cfg = {
@@ -218,7 +212,7 @@ static const struct of_device_id sunxi_sid_of_match[] = {
{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
- { .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg },
+ { .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
--
2.35.1
next prev parent reply other threads:[~2022-08-14 17:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-14 17:36 [PATCH 0/4] nvmem: Support non-stride-aligned NVMEM cell data Samuel Holland
2022-08-14 17:36 ` [PATCH 1/4] nvmem: sunxi_sid: Always use 32-bit MMIO reads Samuel Holland
2022-08-25 12:05 ` Heiko Stübner
2022-09-09 8:48 ` Srinivas Kandagatla
2023-01-08 20:50 ` Jernej Škrabec
2022-08-14 17:36 ` Samuel Holland [this message]
2022-08-15 8:37 ` [PATCH 2/4] nvmem: sunxi_sid: Drop the workaround on A64 Icenowy Zheng
2022-08-16 0:16 ` Samuel Holland
2022-08-14 17:36 ` [PATCH 3/4] dt-bindings: nvmem: Allow bit offsets greater than a byte Samuel Holland
2022-08-25 21:02 ` Rob Herring
2022-09-09 3:29 ` Samuel Holland
2023-01-01 18:59 ` Samuel Holland
2022-08-14 17:36 ` [PATCH 4/4] nvmem: core: Support reading cells with >= 8 bit offsets Samuel Holland
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