From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Robert Richter <rrichter@amd.com>
Subject: [PATCH 04/15] cxl: Unify debug messages when calling devm_cxl_add_dport()
Date: Wed, 31 Aug 2022 10:15:52 +0200 [thread overview]
Message-ID: <20220831081603.3415-5-rrichter@amd.com> (raw)
In-Reply-To: <20220831081603.3415-1-rrichter@amd.com>
CXL dports are added in a couple of code paths using
devm_cxl_add_dport(). Debug messages are individually generated, but
are incomplete and inconsistent. Change this by moving its generation
to devm_cxl_add_dport(). This unifies the messages and reduces code
duplication. Also, generate messages on failure.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/acpi.c | 7 ++-----
drivers/cxl/core/pci.c | 2 --
drivers/cxl/core/port.c | 28 ++++++++++++++++++++--------
tools/testing/cxl/test/cxl.c | 8 +-------
4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 767a91f44221..31e104f0210f 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -282,12 +282,9 @@ static int add_host_bridge_dport(struct device *match, void *arg)
}
dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
- if (IS_ERR(dport)) {
- dev_err(host, "failed to add downstream port: %s\n",
- dev_name(match));
+ if (IS_ERR(dport))
return PTR_ERR(dport);
- }
- dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
+
return 0;
}
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 9240df53ed87..0dbbe8d39b07 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -62,8 +62,6 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
}
ctx->count++;
- dev_dbg(&port->dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
-
return 0;
}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 8604cda88787..61e9915162d5 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -914,12 +914,16 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
}
if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", port_id) >=
- CXL_TARGET_STRLEN)
- return ERR_PTR(-EINVAL);
+ CXL_TARGET_STRLEN) {
+ rc = -EINVAL;
+ goto err;
+ }
dport = devm_kzalloc(host, sizeof(*dport), GFP_KERNEL);
- if (!dport)
- return ERR_PTR(-ENOMEM);
+ if (!dport) {
+ rc = -ENOMEM;
+ goto err;
+ }
dport->dport = dport_dev;
dport->port_id = port_id;
@@ -930,22 +934,30 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
rc = add_dport(port, dport);
cond_cxl_root_unlock(port);
if (rc)
- return ERR_PTR(rc);
+ goto err;
get_device(dport_dev);
rc = devm_add_action_or_reset(host, cxl_dport_remove, dport);
if (rc)
- return ERR_PTR(rc);
+ goto err;
rc = sysfs_create_link(&port->dev.kobj, &dport_dev->kobj, link_name);
if (rc)
- return ERR_PTR(rc);
+ goto err;
rc = devm_add_action_or_reset(host, cxl_dport_unlink, dport);
if (rc)
- return ERR_PTR(rc);
+ goto err;
+
+ dev_dbg(&port->dev, "added %s (%s) as dport of device %s\n",
+ dev_name(&port->dev), link_name, dev_name(dport_dev));
return dport;
+err:
+ dev_dbg(&port->dev, "failed to add %s (%s) as dport of device %s: %d\n",
+ dev_name(&port->dev), link_name, dev_name(dport_dev), rc);
+
+ return ERR_PTR(rc);
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, CXL);
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index a072b2d3e726..c610625e8261 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -582,14 +582,8 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
CXL_RESOURCE_NONE);
- if (IS_ERR(dport)) {
- dev_err(dev, "failed to add dport: %s (%ld)\n",
- dev_name(&pdev->dev), PTR_ERR(dport));
+ if (IS_ERR(dport))
return PTR_ERR(dport);
- }
-
- dev_dbg(dev, "add dport%d: %s\n", pdev->id,
- dev_name(&pdev->dev));
}
return 0;
--
2.30.2
next prev parent reply other threads:[~2022-08-31 8:17 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 8:15 [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-08-31 8:15 ` [PATCH 01/15] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-08-31 8:54 ` Jonathan Cameron
2022-09-01 5:21 ` Robert Richter
2022-08-31 9:39 ` kernel test robot
2022-09-07 16:11 ` [PATCH 1/15] " Davidlohr Bueso
2022-09-09 10:38 ` Robert Richter
2022-09-08 5:44 ` [PATCH 01/15] " Dan Williams
2022-09-08 14:51 ` Robert Richter
2022-09-08 19:47 ` Dan Williams
2022-08-31 8:15 ` [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-08-31 8:56 ` Jonathan Cameron
2022-09-01 5:31 ` Robert Richter
2022-09-08 5:48 ` Dan Williams
2022-09-09 12:19 ` Robert Richter
2022-09-16 18:04 ` Dan Williams
2022-09-28 10:28 ` Robert Richter
2022-09-30 19:07 ` Dan Williams
2022-08-31 8:15 ` [PATCH 03/15] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-08-31 9:59 ` Jonathan Cameron
2022-09-01 5:36 ` Robert Richter
2022-09-06 7:30 ` Robert Richter
2022-09-06 8:52 ` Jonathan Cameron
2022-09-07 16:21 ` [PATCH 3/15] " Davidlohr Bueso
2022-09-08 5:53 ` [PATCH 03/15] " Dan Williams
2022-09-28 10:32 ` Robert Richter
2022-08-31 8:15 ` Robert Richter [this message]
2022-09-07 16:29 ` [PATCH 4/15] cxl: Unify debug messages when calling devm_cxl_add_dport() Davidlohr Bueso
2022-09-08 5:55 ` [PATCH 04/15] " Dan Williams
2022-08-31 8:15 ` [PATCH 05/15] cxl/acpi: Add probe function to detect restricted CXL hosts in RCD mode Robert Richter
2022-08-31 10:08 ` Jonathan Cameron
2022-09-01 6:01 ` Robert Richter
2022-09-01 10:10 ` Jonathan Cameron
2022-09-06 7:19 ` Robert Richter
2022-09-06 8:53 ` Jonathan Cameron
2022-09-07 18:22 ` Bjorn Helgaas
2022-09-08 6:00 ` Dan Williams
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 06/15] PCI/ACPI: Link host bridge to its ACPI fw node Robert Richter
2022-08-31 10:11 ` Jonathan Cameron
2022-09-07 18:37 ` Bjorn Helgaas
2022-09-07 20:15 ` Rafael J. Wysocki
2022-09-08 6:05 ` Dan Williams
2022-09-08 13:06 ` Rafael J. Wysocki
2022-09-08 19:45 ` Dan Williams
2022-09-09 10:20 ` Robert Richter
2022-09-14 22:11 ` Bjorn Helgaas
2022-09-16 23:16 ` Dan Williams
2022-09-08 13:04 ` Rafael J. Wysocki
2022-08-31 8:15 ` [PATCH 07/15] cxl/acpi: Check RCH's PCIe Host Bridge ACPI ID Robert Richter
2022-08-31 10:20 ` Jonathan Cameron
2022-09-01 6:16 ` Robert Richter
2022-09-01 10:14 ` Jonathan Cameron
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities Robert Richter
2022-08-31 10:52 ` Jonathan Cameron
2022-08-31 11:12 ` Jonathan Cameron
2022-09-01 6:38 ` Robert Richter
2022-09-01 10:37 ` Jonathan Cameron
2022-09-06 10:20 ` Robert Richter
2022-09-01 6:30 ` Robert Richter
2022-09-01 10:23 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-08-31 8:15 ` [PATCH 09/15] cxl/acpi: Determine PCI host bridge's ACPI UID Robert Richter
2022-08-31 11:00 ` Jonathan Cameron
2022-09-01 6:53 ` Robert Richter
2022-09-01 10:41 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-09-08 20:47 ` Jonathan Zhang (Infra)
2022-09-08 21:10 ` Dan Williams
2022-09-08 21:35 ` Jonathan Zhang (Infra)
2022-09-08 22:31 ` Dan Williams
2022-09-08 22:41 ` Jonathan Zhang (Infra)
2022-08-31 8:15 ` [PATCH 10/15] cxl/acpi: Extract the RCH's RCRB base address from CEDT Robert Richter
2022-08-31 11:09 ` Jonathan Cameron
2022-09-01 7:04 ` Robert Richter
2022-08-31 8:15 ` [PATCH 11/15] cxl/acpi: Extract the host's component register base address from RCRB Robert Richter
2022-08-31 11:56 ` Jonathan Cameron
2022-09-01 7:38 ` Robert Richter
2022-09-01 11:00 ` Jonathan Cameron
2022-09-06 11:32 ` Robert Richter
2022-09-08 20:59 ` Jonathan Zhang (Infra)
2022-08-31 8:16 ` [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode Robert Richter
2022-08-31 11:58 ` Jonathan Cameron
2022-09-01 7:40 ` Robert Richter
2022-08-31 8:16 ` [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support " Robert Richter
2022-08-31 12:11 ` Jonathan Cameron
2022-09-01 7:50 ` Robert Richter
2022-08-31 8:16 ` [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs Robert Richter
2022-08-31 12:16 ` Jonathan Cameron
2022-09-01 7:54 ` Robert Richter
2022-08-31 8:16 ` [PATCH 15/15] cxl/acpi: Specify module load order dependency for the cxl_acpi module Robert Richter
2022-09-16 18:12 ` Dan Williams
2022-08-31 12:23 ` [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Jonathan Cameron
2022-09-01 8:19 ` Robert Richter
2022-09-08 6:41 ` Dan Williams
2022-09-08 5:43 ` Dan Williams
2022-09-08 18:52 ` Jonathan Zhang (Infra)
2022-09-08 19:51 ` Dan Williams
2022-09-08 20:36 ` Jonathan Zhang (Infra)
2022-09-08 21:02 ` Dan Williams
2022-09-16 18:16 ` Dan Williams
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