From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>
Subject: Re: [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode
Date: Wed, 31 Aug 2022 12:58:30 +0100 [thread overview]
Message-ID: <20220831125830.00005105@huawei.com> (raw)
In-Reply-To: <20220831081603.3415-13-rrichter@amd.com>
On Wed, 31 Aug 2022 10:16:00 +0200
Robert Richter <rrichter@amd.com> wrote:
> RCD mode has a different enumeration scheme other than in CXL VH mode.
> An RCD is directly connected to an RCH without downstream and upstream
> ports showing up in between in the PCI hierarchy. Skip dport
> enumeration for RCHs. Upstream and downstream ports of RCH and RCD
> will be setup separately in a later patch.
>
> Introduce the function is_rch_uport() to detect an RCH port. For RCHs
> the parent root port is not the "ACPI0017" device and instead does not
> have a fw node connected to it.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
> drivers/cxl/core/pci.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 0dbbe8d39b07..86ed112eb262 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -65,6 +65,15 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
> return 0;
> }
>
> +/*
> + * A parent of an RCH (CXL 1.1 host) is a plain platform device while
> + * a 2.0 host links to the ACPI0017 root device.
> + */
> +static inline bool is_rch_uport(struct cxl_port *port)
> +{
> + return is_cxl_port(&port->dev) && !port->dev.parent->fwnode;
I'm not keen on the presence of fwnode being used to distinguish anything.
That's the sort of thing that gets 'fixed' by later patches.
Can we check something more specific?
> +}
> +
> /**
> * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
> * @port: cxl_port whose ->uport is the upstream of dports to be enumerated
> @@ -74,10 +83,19 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
> */
> int devm_cxl_port_enumerate_dports(struct cxl_port *port)
> {
> - struct pci_bus *bus = cxl_port_to_pci_bus(port);
> + struct pci_bus *bus;
> struct cxl_walk_context ctx;
> int type;
>
> + /*
> + * Skip enumeration in Restricted CXL Device mode as the
> + * device has been already registered at the host's dport
> + * during host discovery.
> + */
> + if (is_rch_uport(port))
> + return 0;
> +
> + bus = cxl_port_to_pci_bus(port);
> if (!bus)
> return -ENXIO;
>
next prev parent reply other threads:[~2022-08-31 11:58 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 8:15 [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-08-31 8:15 ` [PATCH 01/15] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-08-31 8:54 ` Jonathan Cameron
2022-09-01 5:21 ` Robert Richter
2022-08-31 9:39 ` kernel test robot
2022-09-07 16:11 ` [PATCH 1/15] " Davidlohr Bueso
2022-09-09 10:38 ` Robert Richter
2022-09-08 5:44 ` [PATCH 01/15] " Dan Williams
2022-09-08 14:51 ` Robert Richter
2022-09-08 19:47 ` Dan Williams
2022-08-31 8:15 ` [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-08-31 8:56 ` Jonathan Cameron
2022-09-01 5:31 ` Robert Richter
2022-09-08 5:48 ` Dan Williams
2022-09-09 12:19 ` Robert Richter
2022-09-16 18:04 ` Dan Williams
2022-09-28 10:28 ` Robert Richter
2022-09-30 19:07 ` Dan Williams
2022-08-31 8:15 ` [PATCH 03/15] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-08-31 9:59 ` Jonathan Cameron
2022-09-01 5:36 ` Robert Richter
2022-09-06 7:30 ` Robert Richter
2022-09-06 8:52 ` Jonathan Cameron
2022-09-07 16:21 ` [PATCH 3/15] " Davidlohr Bueso
2022-09-08 5:53 ` [PATCH 03/15] " Dan Williams
2022-09-28 10:32 ` Robert Richter
2022-08-31 8:15 ` [PATCH 04/15] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-09-07 16:29 ` [PATCH 4/15] " Davidlohr Bueso
2022-09-08 5:55 ` [PATCH 04/15] " Dan Williams
2022-08-31 8:15 ` [PATCH 05/15] cxl/acpi: Add probe function to detect restricted CXL hosts in RCD mode Robert Richter
2022-08-31 10:08 ` Jonathan Cameron
2022-09-01 6:01 ` Robert Richter
2022-09-01 10:10 ` Jonathan Cameron
2022-09-06 7:19 ` Robert Richter
2022-09-06 8:53 ` Jonathan Cameron
2022-09-07 18:22 ` Bjorn Helgaas
2022-09-08 6:00 ` Dan Williams
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 06/15] PCI/ACPI: Link host bridge to its ACPI fw node Robert Richter
2022-08-31 10:11 ` Jonathan Cameron
2022-09-07 18:37 ` Bjorn Helgaas
2022-09-07 20:15 ` Rafael J. Wysocki
2022-09-08 6:05 ` Dan Williams
2022-09-08 13:06 ` Rafael J. Wysocki
2022-09-08 19:45 ` Dan Williams
2022-09-09 10:20 ` Robert Richter
2022-09-14 22:11 ` Bjorn Helgaas
2022-09-16 23:16 ` Dan Williams
2022-09-08 13:04 ` Rafael J. Wysocki
2022-08-31 8:15 ` [PATCH 07/15] cxl/acpi: Check RCH's PCIe Host Bridge ACPI ID Robert Richter
2022-08-31 10:20 ` Jonathan Cameron
2022-09-01 6:16 ` Robert Richter
2022-09-01 10:14 ` Jonathan Cameron
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities Robert Richter
2022-08-31 10:52 ` Jonathan Cameron
2022-08-31 11:12 ` Jonathan Cameron
2022-09-01 6:38 ` Robert Richter
2022-09-01 10:37 ` Jonathan Cameron
2022-09-06 10:20 ` Robert Richter
2022-09-01 6:30 ` Robert Richter
2022-09-01 10:23 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-08-31 8:15 ` [PATCH 09/15] cxl/acpi: Determine PCI host bridge's ACPI UID Robert Richter
2022-08-31 11:00 ` Jonathan Cameron
2022-09-01 6:53 ` Robert Richter
2022-09-01 10:41 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-09-08 20:47 ` Jonathan Zhang (Infra)
2022-09-08 21:10 ` Dan Williams
2022-09-08 21:35 ` Jonathan Zhang (Infra)
2022-09-08 22:31 ` Dan Williams
2022-09-08 22:41 ` Jonathan Zhang (Infra)
2022-08-31 8:15 ` [PATCH 10/15] cxl/acpi: Extract the RCH's RCRB base address from CEDT Robert Richter
2022-08-31 11:09 ` Jonathan Cameron
2022-09-01 7:04 ` Robert Richter
2022-08-31 8:15 ` [PATCH 11/15] cxl/acpi: Extract the host's component register base address from RCRB Robert Richter
2022-08-31 11:56 ` Jonathan Cameron
2022-09-01 7:38 ` Robert Richter
2022-09-01 11:00 ` Jonathan Cameron
2022-09-06 11:32 ` Robert Richter
2022-09-08 20:59 ` Jonathan Zhang (Infra)
2022-08-31 8:16 ` [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode Robert Richter
2022-08-31 11:58 ` Jonathan Cameron [this message]
2022-09-01 7:40 ` Robert Richter
2022-08-31 8:16 ` [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support " Robert Richter
2022-08-31 12:11 ` Jonathan Cameron
2022-09-01 7:50 ` Robert Richter
2022-08-31 8:16 ` [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs Robert Richter
2022-08-31 12:16 ` Jonathan Cameron
2022-09-01 7:54 ` Robert Richter
2022-08-31 8:16 ` [PATCH 15/15] cxl/acpi: Specify module load order dependency for the cxl_acpi module Robert Richter
2022-09-16 18:12 ` Dan Williams
2022-08-31 12:23 ` [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Jonathan Cameron
2022-09-01 8:19 ` Robert Richter
2022-09-08 6:41 ` Dan Williams
2022-09-08 5:43 ` Dan Williams
2022-09-08 18:52 ` Jonathan Zhang (Infra)
2022-09-08 19:51 ` Dan Williams
2022-09-08 20:36 ` Jonathan Zhang (Infra)
2022-09-08 21:02 ` Dan Williams
2022-09-16 18:16 ` Dan Williams
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