* [PATCH -next] drm/amd/display: clean up some inconsistent indentings
@ 2022-09-01 7:56 Yang Li
2022-09-09 20:41 ` Alex Deucher
0 siblings, 1 reply; 6+ messages in thread
From: Yang Li @ 2022-09-01 7:56 UTC (permalink / raw)
To: alexander.deucher
Cc: harry.wentland, sunpeng.li, Rodrigo.Siqueira, christian.koenig,
Xinhui.Pan, airlied, daniel, amd-gfx, dri-devel, linux-kernel,
Yang Li, Abaci Robot
This if statement is the content of the for statement above it. It
should be indented.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2026
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 9dd705b985b9..0139e98a0aa1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -417,8 +417,8 @@ void get_subvp_visual_confirm_color(
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
- if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
- pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+ if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
+ pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
/* SubVP enable - red */
color->color_r_cr = color_value;
enable_subvp = true;
--
2.20.1.7.g153144c
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH -next] drm/amd/display: clean up some inconsistent indentings
2022-09-01 7:56 [PATCH -next] drm/amd/display: clean up some inconsistent indentings Yang Li
@ 2022-09-09 20:41 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2022-09-09 20:41 UTC (permalink / raw)
To: Yang Li
Cc: alexander.deucher, sunpeng.li, Abaci Robot, Xinhui.Pan,
Rodrigo.Siqueira, linux-kernel, amd-gfx, airlied, dri-devel,
christian.koenig
Applied. Thanks!
Alex
On Thu, Sep 1, 2022 at 3:57 AM Yang Li <yang.lee@linux.alibaba.com> wrote:
>
> This if statement is the content of the for statement above it. It
> should be indented.
>
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2026
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> index 9dd705b985b9..0139e98a0aa1 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
> @@ -417,8 +417,8 @@ void get_subvp_visual_confirm_color(
> for (i = 0; i < dc->res_pool->pipe_count; i++) {
> struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
>
> - if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
> - pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
> + if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
> + pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
> /* SubVP enable - red */
> color->color_r_cr = color_value;
> enable_subvp = true;
> --
> 2.20.1.7.g153144c
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH -next] drm/amd/display: clean up some inconsistent indentings
@ 2023-02-10 1:05 Yang Li
2023-02-13 16:14 ` Alex Deucher
0 siblings, 1 reply; 6+ messages in thread
From: Yang Li @ 2023-02-10 1:05 UTC (permalink / raw)
To: alexander.deucher
Cc: harry.wentland, sunpeng.li, Rodrigo.Siqueira, christian.koenig,
Xinhui.Pan, airlied, daniel, amd-gfx, dri-devel, linux-kernel,
Yang Li, Abaci Robot
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:145 get_ddc_line() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:201 dc_link_construct_phy() warn: inconsistent indenting
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4026
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
drivers/gpu/drm/amd/display/dc/link/link_factory.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 13a766273755..23f668d90460 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -142,7 +142,7 @@ static enum channel_id get_ddc_line(struct dc_link *link)
struct ddc *ddc;
enum channel_id channel;
- channel = CHANNEL_ID_UNKNOWN;
+ channel = CHANNEL_ID_UNKNOWN;
ddc = get_ddc_pin(link->ddc);
@@ -196,8 +196,8 @@ static bool dc_link_construct_phy(struct dc_link *link,
DC_LOGGER_INIT(dc_ctx->logger);
- link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
- link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
+ link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
+ link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
link->link_status.dpcd_caps = &link->dpcd_caps;
link->dc = init_params->dc;
--
2.20.1.7.g153144c
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH -next] drm/amd/display: clean up some inconsistent indentings
2023-02-10 1:05 Yang Li
@ 2023-02-13 16:14 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2023-02-13 16:14 UTC (permalink / raw)
To: Yang Li
Cc: alexander.deucher, sunpeng.li, Xinhui.Pan, Rodrigo.Siqueira,
linux-kernel, amd-gfx, Abaci Robot, dri-devel, christian.koenig
Applied. Thanks!
On Thu, Feb 9, 2023 at 8:06 PM Yang Li <yang.lee@linux.alibaba.com> wrote:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:145 get_ddc_line() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:201 dc_link_construct_phy() warn: inconsistent indenting
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4026
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
> drivers/gpu/drm/amd/display/dc/link/link_factory.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> index 13a766273755..23f668d90460 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
> @@ -142,7 +142,7 @@ static enum channel_id get_ddc_line(struct dc_link *link)
> struct ddc *ddc;
> enum channel_id channel;
>
> - channel = CHANNEL_ID_UNKNOWN;
> + channel = CHANNEL_ID_UNKNOWN;
>
> ddc = get_ddc_pin(link->ddc);
>
> @@ -196,8 +196,8 @@ static bool dc_link_construct_phy(struct dc_link *link,
>
> DC_LOGGER_INIT(dc_ctx->logger);
>
> - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
> - link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
> + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
> + link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
> link->link_status.dpcd_caps = &link->dpcd_caps;
>
> link->dc = init_params->dc;
> --
> 2.20.1.7.g153144c
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH -next] drm/amd/display: clean up some inconsistent indentings
@ 2023-09-28 1:13 Yang Li
2023-10-18 13:54 ` Alex Deucher
0 siblings, 1 reply; 6+ messages in thread
From: Yang Li @ 2023-09-28 1:13 UTC (permalink / raw)
To: alexander.deucher, airlied, daniel
Cc: amd-gfx, dri-devel, linux-kernel, Yang Li
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn35/dcn35_fpu.c:261 dcn35_update_bw_bounding_box_fpu() warn: inconsistent indenting
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 144 +++++++++---------
1 file changed, 72 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 4d5ee2aad9e4..4f284c31de5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -258,85 +258,85 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
dc_assert_fp_enabled();
- dcn3_5_ip.max_num_otg =
- dc->res_pool->res_cap->num_timing_generator;
- dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
- dcn3_5_soc.num_chans = bw_params->num_channels;
-
- ASSERT(clk_table->num_entries);
-
- /* Prepass to find max clocks independent of voltage level. */
- for (i = 0; i < clk_table->num_entries; ++i) {
- if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
- max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
- if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
- max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
- }
+ dcn3_5_ip.max_num_otg =
+ dc->res_pool->res_cap->num_timing_generator;
+ dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
+ dcn3_5_soc.num_chans = bw_params->num_channels;
+
+ ASSERT(clk_table->num_entries);
+
+ /* Prepass to find max clocks independent of voltage level. */
+ for (i = 0; i < clk_table->num_entries; ++i) {
+ if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
+ max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
+ if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
+ max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
+ }
- for (i = 0; i < clk_table->num_entries; i++) {
- /* loop backwards*/
- for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1;
- j >= 0; j--) {
- if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=
- clk_table->entries[i].dcfclk_mhz) {
- closest_clk_lvl = j;
- break;
- }
- }
- if (clk_table->num_entries == 1) {
- /*smu gives one DPM level, let's take the highest one*/
- closest_clk_lvl = dcn3_5_soc.num_states - 1;
+ for (i = 0; i < clk_table->num_entries; i++) {
+ /* loop backwards*/
+ for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1;
+ j >= 0; j--) {
+ if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=
+ clk_table->entries[i].dcfclk_mhz) {
+ closest_clk_lvl = j;
+ break;
}
+ }
+ if (clk_table->num_entries == 1) {
+ /*smu gives one DPM level, let's take the highest one*/
+ closest_clk_lvl = dcn3_5_soc.num_states - 1;
+ }
- clock_limits[i].state = i;
-
- /* Clocks dependent on voltage level. */
- clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
- if (clk_table->num_entries == 1 &&
- clock_limits[i].dcfclk_mhz <
- dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
- /*SMU fix not released yet*/
- clock_limits[i].dcfclk_mhz =
- dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
- }
+ clock_limits[i].state = i;
- clock_limits[i].fabricclk_mhz =
- clk_table->entries[i].fclk_mhz;
- clock_limits[i].socclk_mhz =
- clk_table->entries[i].socclk_mhz;
-
- if (clk_table->entries[i].memclk_mhz &&
- clk_table->entries[i].wck_ratio)
- clock_limits[i].dram_speed_mts =
- clk_table->entries[i].memclk_mhz * 2 *
- clk_table->entries[i].wck_ratio;
-
- /* Clocks independent of voltage level. */
- clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
- max_dispclk_mhz :
- dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-
- clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
- max_dppclk_mhz :
- dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-
- clock_limits[i].dram_bw_per_chan_gbps =
- dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[i].dscclk_mhz =
- dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[i].dtbclk_mhz =
- dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[i].phyclk_d18_mhz =
- dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[i].phyclk_mhz =
- dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ /* Clocks dependent on voltage level. */
+ clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ if (clk_table->num_entries == 1 &&
+ clock_limits[i].dcfclk_mhz <
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
+ /*SMU fix not released yet*/
+ clock_limits[i].dcfclk_mhz =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
}
- memcpy(dcn3_5_soc.clock_limits, clock_limits,
- sizeof(dcn3_5_soc.clock_limits));
+ clock_limits[i].fabricclk_mhz =
+ clk_table->entries[i].fclk_mhz;
+ clock_limits[i].socclk_mhz =
+ clk_table->entries[i].socclk_mhz;
+
+ if (clk_table->entries[i].memclk_mhz &&
+ clk_table->entries[i].wck_ratio)
+ clock_limits[i].dram_speed_mts =
+ clk_table->entries[i].memclk_mhz * 2 *
+ clk_table->entries[i].wck_ratio;
+
+ /* Clocks independent of voltage level. */
+ clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
+ max_dispclk_mhz :
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+
+ clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
+ max_dppclk_mhz :
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+
+ clock_limits[i].dram_bw_per_chan_gbps =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+ clock_limits[i].dscclk_mhz =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+ clock_limits[i].dtbclk_mhz =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+ clock_limits[i].phyclk_d18_mhz =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+ clock_limits[i].phyclk_mhz =
+ dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ }
+
+ memcpy(dcn3_5_soc.clock_limits, clock_limits,
+ sizeof(dcn3_5_soc.clock_limits));
- if (clk_table->num_entries)
- dcn3_5_soc.num_states = clk_table->num_entries;
+ if (clk_table->num_entries)
+ dcn3_5_soc.num_states = clk_table->num_entries;
if (max_dispclk_mhz) {
dcn3_5_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
--
2.20.1.7.g153144c
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH -next] drm/amd/display: clean up some inconsistent indentings
2023-09-28 1:13 Yang Li
@ 2023-10-18 13:54 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2023-10-18 13:54 UTC (permalink / raw)
To: Yang Li
Cc: alexander.deucher, airlied, daniel, dri-devel, amd-gfx, linux-kernel
Applied. Thanks!
On Wed, Sep 27, 2023 at 9:14 PM Yang Li <yang.lee@linux.alibaba.com> wrote:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn35/dcn35_fpu.c:261 dcn35_update_bw_bounding_box_fpu() warn: inconsistent indenting
>
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
> .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 144 +++++++++---------
> 1 file changed, 72 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
> index 4d5ee2aad9e4..4f284c31de5d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
> @@ -258,85 +258,85 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
>
> dc_assert_fp_enabled();
>
> - dcn3_5_ip.max_num_otg =
> - dc->res_pool->res_cap->num_timing_generator;
> - dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
> - dcn3_5_soc.num_chans = bw_params->num_channels;
> -
> - ASSERT(clk_table->num_entries);
> -
> - /* Prepass to find max clocks independent of voltage level. */
> - for (i = 0; i < clk_table->num_entries; ++i) {
> - if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
> - max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
> - if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
> - max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
> - }
> + dcn3_5_ip.max_num_otg =
> + dc->res_pool->res_cap->num_timing_generator;
> + dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
> + dcn3_5_soc.num_chans = bw_params->num_channels;
> +
> + ASSERT(clk_table->num_entries);
> +
> + /* Prepass to find max clocks independent of voltage level. */
> + for (i = 0; i < clk_table->num_entries; ++i) {
> + if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
> + max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
> + if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
> + max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
> + }
>
> - for (i = 0; i < clk_table->num_entries; i++) {
> - /* loop backwards*/
> - for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1;
> - j >= 0; j--) {
> - if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=
> - clk_table->entries[i].dcfclk_mhz) {
> - closest_clk_lvl = j;
> - break;
> - }
> - }
> - if (clk_table->num_entries == 1) {
> - /*smu gives one DPM level, let's take the highest one*/
> - closest_clk_lvl = dcn3_5_soc.num_states - 1;
> + for (i = 0; i < clk_table->num_entries; i++) {
> + /* loop backwards*/
> + for (closest_clk_lvl = 0, j = dcn3_5_soc.num_states - 1;
> + j >= 0; j--) {
> + if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=
> + clk_table->entries[i].dcfclk_mhz) {
> + closest_clk_lvl = j;
> + break;
> }
> + }
> + if (clk_table->num_entries == 1) {
> + /*smu gives one DPM level, let's take the highest one*/
> + closest_clk_lvl = dcn3_5_soc.num_states - 1;
> + }
>
> - clock_limits[i].state = i;
> -
> - /* Clocks dependent on voltage level. */
> - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> - if (clk_table->num_entries == 1 &&
> - clock_limits[i].dcfclk_mhz <
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
> - /*SMU fix not released yet*/
> - clock_limits[i].dcfclk_mhz =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
> - }
> + clock_limits[i].state = i;
>
> - clock_limits[i].fabricclk_mhz =
> - clk_table->entries[i].fclk_mhz;
> - clock_limits[i].socclk_mhz =
> - clk_table->entries[i].socclk_mhz;
> -
> - if (clk_table->entries[i].memclk_mhz &&
> - clk_table->entries[i].wck_ratio)
> - clock_limits[i].dram_speed_mts =
> - clk_table->entries[i].memclk_mhz * 2 *
> - clk_table->entries[i].wck_ratio;
> -
> - /* Clocks independent of voltage level. */
> - clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
> - max_dispclk_mhz :
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> -
> - clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
> - max_dppclk_mhz :
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> -
> - clock_limits[i].dram_bw_per_chan_gbps =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> - clock_limits[i].dscclk_mhz =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> - clock_limits[i].dtbclk_mhz =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> - clock_limits[i].phyclk_d18_mhz =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> - clock_limits[i].phyclk_mhz =
> - dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + /* Clocks dependent on voltage level. */
> + clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> + if (clk_table->num_entries == 1 &&
> + clock_limits[i].dcfclk_mhz <
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
> + /*SMU fix not released yet*/
> + clock_limits[i].dcfclk_mhz =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
> }
>
> - memcpy(dcn3_5_soc.clock_limits, clock_limits,
> - sizeof(dcn3_5_soc.clock_limits));
> + clock_limits[i].fabricclk_mhz =
> + clk_table->entries[i].fclk_mhz;
> + clock_limits[i].socclk_mhz =
> + clk_table->entries[i].socclk_mhz;
> +
> + if (clk_table->entries[i].memclk_mhz &&
> + clk_table->entries[i].wck_ratio)
> + clock_limits[i].dram_speed_mts =
> + clk_table->entries[i].memclk_mhz * 2 *
> + clk_table->entries[i].wck_ratio;
> +
> + /* Clocks independent of voltage level. */
> + clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
> + max_dispclk_mhz :
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> +
> + clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
> + max_dppclk_mhz :
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> +
> + clock_limits[i].dram_bw_per_chan_gbps =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> + clock_limits[i].dscclk_mhz =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> + clock_limits[i].dtbclk_mhz =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> + clock_limits[i].phyclk_d18_mhz =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> + clock_limits[i].phyclk_mhz =
> + dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + }
> +
> + memcpy(dcn3_5_soc.clock_limits, clock_limits,
> + sizeof(dcn3_5_soc.clock_limits));
>
> - if (clk_table->num_entries)
> - dcn3_5_soc.num_states = clk_table->num_entries;
> + if (clk_table->num_entries)
> + dcn3_5_soc.num_states = clk_table->num_entries;
>
> if (max_dispclk_mhz) {
> dcn3_5_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
> --
> 2.20.1.7.g153144c
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-10-18 13:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-01 7:56 [PATCH -next] drm/amd/display: clean up some inconsistent indentings Yang Li
2022-09-09 20:41 ` Alex Deucher
2023-02-10 1:05 Yang Li
2023-02-13 16:14 ` Alex Deucher
2023-09-28 1:13 Yang Li
2023-10-18 13:54 ` Alex Deucher
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