From: Andrew Jones <ajones@ventanamicro.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/3] riscv: kvm: use generic entry for TIF_NOTIFY_RESUME and misc
Date: Wed, 28 Sep 2022 11:00:12 +0200 [thread overview]
Message-ID: <20220928090012.gjh3ftvkpus5df63@kamzik> (raw)
In-Reply-To: <20220925162400.1606-1-jszhang@kernel.org>
On Mon, Sep 26, 2022 at 12:23:57AM +0800, Jisheng Zhang wrote:
> This series is a preparation series to add PREEMPT_RT support to riscv:
> patch1 adds the missing number of signal exits in vCPU stat
> patch2 switches to the generic guest entry infrastructure
> patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for
> RT
>
> After these three patches merged, the left RT patches are similar as
> other arch.
>
> Since v2:
> - splict the series into two separate ones, one for next another for
> RT.
>
> Since v1:
> - send to related maillist, I press ENTER too quickly when sending v1
> - remove the signal_pending() handling because that's covered by
> generic guest entry infrastructure
>
> Jisheng Zhang (3):
> RISC-V: KVM: Record number of signal exits as a vCPU stat
> RISC-V: KVM: Use generic guest entry infrastructure
> riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
>
> arch/riscv/Kconfig | 1 +
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/Kconfig | 1 +
> arch/riscv/kvm/vcpu.c | 18 +++++++-----------
> 4 files changed, 10 insertions(+), 11 deletions(-)
>
> --
> 2.34.1
>
For the series
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2022-09-28 9:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-25 16:23 [PATCH v3 0/3] riscv: kvm: use generic entry for TIF_NOTIFY_RESUME and misc Jisheng Zhang
2022-09-25 16:23 ` [PATCH v3 1/3] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang
2022-09-28 5:18 ` Guo Ren
2022-09-28 8:59 ` Andrew Jones
2022-09-25 16:23 ` [PATCH v3 2/3] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang
2022-09-25 16:24 ` [PATCH v3 3/3] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Jisheng Zhang
2022-09-28 9:00 ` Andrew Jones [this message]
2022-10-01 12:37 ` [PATCH v3 0/3] riscv: kvm: use generic entry for TIF_NOTIFY_RESUME and misc Anup Patel
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