* [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data
2022-09-30 9:59 [PATCH v7, 0/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
@ 2022-09-30 9:59 ` Yongqiang Niu
2022-09-30 13:20 ` Matthias Brugger
2022-09-30 9:59 ` [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow Yongqiang Niu
2022-09-30 9:59 ` [PATCH v7, 3/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
2 siblings, 1 reply; 6+ messages in thread
From: Yongqiang Niu @ 2022-09-30 9:59 UTC (permalink / raw)
To: CK Hu, Chun-Kuang Hu
Cc: Jassi Brar, Matthias Brugger, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Yongqiang Niu
if gce work control by software, we need set software enable
for MT8186 Soc
there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9465f9081515..04eb44d89119 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -38,6 +38,8 @@
#define CMDQ_THR_PRIORITY 0x40
#define GCE_GCTL_VALUE 0x48
+#define GCE_CTRL_BY_SW GENMASK(2, 0)
+#define GCE_DDR_EN GENMASK(18, 16)
#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
#define CMDQ_THR_ENABLED 0x1
@@ -80,6 +82,7 @@ struct cmdq {
bool suspended;
u8 shift_pa;
bool control_by_sw;
+ bool sw_ddr_en;
u32 gce_num;
};
@@ -87,6 +90,7 @@ struct gce_plat {
u32 thread_nr;
u8 shift;
bool control_by_sw;
+ bool sw_ddr_en;
u32 gce_num;
};
@@ -129,7 +133,11 @@ static void cmdq_init(struct cmdq *cmdq)
WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
if (cmdq->control_by_sw)
- writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+ writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
+ if (cmdq->sw_ddr_en)
+ writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
for (i = 0; i <= CMDQ_MAX_EVENT; i++)
writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
@@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev)
cmdq->thread_nr = plat_data->thread_nr;
cmdq->shift_pa = plat_data->shift;
cmdq->control_by_sw = plat_data->control_by_sw;
+ cmdq->sw_ddr_en = plat_data->sw_ddr_en;
cmdq->gce_num = plat_data->gce_num;
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data
2022-09-30 9:59 ` [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data Yongqiang Niu
@ 2022-09-30 13:20 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2022-09-30 13:20 UTC (permalink / raw)
To: Yongqiang Niu, CK Hu, Chun-Kuang Hu
Cc: Jassi Brar, linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On 30/09/2022 11:59, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
>
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..04eb44d89119 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -38,6 +38,8 @@
> #define CMDQ_THR_PRIORITY 0x40
>
> #define GCE_GCTL_VALUE 0x48
> +#define GCE_CTRL_BY_SW GENMASK(2, 0)
> +#define GCE_DDR_EN GENMASK(18, 16)
>
> #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
> #define CMDQ_THR_ENABLED 0x1
> @@ -80,6 +82,7 @@ struct cmdq {
> bool suspended;
> u8 shift_pa;
> bool control_by_sw;
> + bool sw_ddr_en;
> u32 gce_num;
> };
>
> @@ -87,6 +90,7 @@ struct gce_plat {
> u32 thread_nr;
> u8 shift;
> bool control_by_sw;
> + bool sw_ddr_en;
> u32 gce_num;
> };
>
> @@ -129,7 +133,11 @@ static void cmdq_init(struct cmdq *cmdq)
>
> WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> if (cmdq->control_by_sw)
> - writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
Thanks for doing this, but I think this should be part of a seperate patch. It's
a cleanup and has nothing to do with the new sw_ddr_en, correct?
Regards,
Matthias
> +
> + if (cmdq->sw_ddr_en)
> + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
> writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
> for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev)
> cmdq->thread_nr = plat_data->thread_nr;
> cmdq->shift_pa = plat_data->shift;
> cmdq->control_by_sw = plat_data->control_by_sw;
> + cmdq->sw_ddr_en = plat_data->sw_ddr_en;
> cmdq->gce_num = plat_data->gce_num;
> cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow
2022-09-30 9:59 [PATCH v7, 0/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
2022-09-30 9:59 ` [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data Yongqiang Niu
@ 2022-09-30 9:59 ` Yongqiang Niu
2022-09-30 13:18 ` Matthias Brugger
2022-09-30 9:59 ` [PATCH v7, 3/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
2 siblings, 1 reply; 6+ messages in thread
From: Yongqiang Niu @ 2022-09-30 9:59 UTC (permalink / raw)
To: CK Hu, Chun-Kuang Hu
Cc: Jassi Brar, Matthias Brugger, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Yongqiang Niu
add gce ddr enable control flow when gce suspend/resume
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 04eb44d89119..84a60750d0c4 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -94,6 +94,21 @@ struct gce_plat {
u32 gce_num;
};
+static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
+{
+ if (!cmdq->sw_ddr_en)
+ return;
+
+ WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+
+ if (enable)
+ writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+ else
+ writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
+ clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+}
+
u8 cmdq_get_shift_pa(struct mbox_chan *chan)
{
struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
@@ -319,6 +334,8 @@ static int cmdq_suspend(struct device *dev)
if (task_running)
dev_warn(dev, "exist running task(s) in suspend\n");
+ cmdq_sw_ddr_enable(cmdq, false);
+
clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
return 0;
@@ -330,6 +347,9 @@ static int cmdq_resume(struct device *dev)
WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
cmdq->suspended = false;
+
+ cmdq_sw_ddr_enable(cmdq, true);
+
return 0;
}
@@ -337,6 +357,8 @@ static int cmdq_remove(struct platform_device *pdev)
{
struct cmdq *cmdq = platform_get_drvdata(pdev);
+ cmdq_sw_ddr_enable(cmdq, false);
+
clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow
2022-09-30 9:59 ` [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow Yongqiang Niu
@ 2022-09-30 13:18 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2022-09-30 13:18 UTC (permalink / raw)
To: Yongqiang Niu, CK Hu, Chun-Kuang Hu
Cc: Jassi Brar, linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On 30/09/2022 11:59, Yongqiang Niu wrote:
> add gce ddr enable control flow when gce suspend/resume
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 04eb44d89119..84a60750d0c4 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,21 @@ struct gce_plat {
> u32 gce_num;
> };
>
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> + if (!cmdq->sw_ddr_en)
> + return;
> +
> + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> + if (enable)
> + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> + else
> + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
> + clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> +}
> +
> u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> {
> struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> @@ -319,6 +334,8 @@ static int cmdq_suspend(struct device *dev)
> if (task_running)
> dev_warn(dev, "exist running task(s) in suspend\n");
>
> + cmdq_sw_ddr_enable(cmdq, false);
I'd say
if (!cmdq->sw_ddr_en)
should be checked before calling cmdq_sw_ddr_enable().
Regards,
Matthias
> +
> clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>
> return 0;
> @@ -330,6 +347,9 @@ static int cmdq_resume(struct device *dev)
>
> WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
> cmdq->suspended = false;
> +
> + cmdq_sw_ddr_enable(cmdq, true);
> +
> return 0;
> }
>
> @@ -337,6 +357,8 @@ static int cmdq_remove(struct platform_device *pdev)
> {
> struct cmdq *cmdq = platform_get_drvdata(pdev);
>
> + cmdq_sw_ddr_enable(cmdq, false);
> +
> clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> return 0;
> }
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v7, 3/3] mailbox: mtk-cmdq: add MT8186 support
2022-09-30 9:59 [PATCH v7, 0/3] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu
2022-09-30 9:59 ` [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data Yongqiang Niu
2022-09-30 9:59 ` [PATCH v7, 2/3] mailbox: mtk-cmdq: add gce ddr enable support flow Yongqiang Niu
@ 2022-09-30 9:59 ` Yongqiang Niu
2 siblings, 0 replies; 6+ messages in thread
From: Yongqiang Niu @ 2022-09-30 9:59 UTC (permalink / raw)
To: CK Hu, Chun-Kuang Hu
Cc: Jassi Brar, Matthias Brugger, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Yongqiang Niu
add MT8186 cmdq support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 84a60750d0c4..ce3c595353d7 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -691,9 +691,18 @@ static const struct gce_plat gce_plat_v6 = {
.gce_num = 2
};
+static const struct gce_plat gce_plat_v7 = {
+ .thread_nr = 24,
+ .shift = 3,
+ .control_by_sw = true,
+ .sw_ddr_en = true,
+ .gce_num = 1
+};
+
static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+ {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread