From: Heiko Stuebner <heiko@sntech.de>
To: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org,
mark.rutland@arm.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Conor.Dooley@microchip.com, cmuellner@linux.com,
samuel@sholland.org, Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH 1/2] RISC-V: Cache SBI vendor values
Date: Tue, 4 Oct 2022 22:37:23 +0200 [thread overview]
Message-ID: <20221004203724.1459763-2-heiko@sntech.de> (raw)
In-Reply-To: <20221004203724.1459763-1-heiko@sntech.de>
sbi_get_mvendorid(), sbi_get_marchid() and sbi_get_mimpid() might get
called multiple times, though the values of these CSRs should not change
during the runtime of a specific machine.
So cache the values in the functions and prevent multiple ecalls
to read these values.
Suggested-by: Atish Patra <atishp@atishpatra.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/kernel/sbi.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422..5be8f90f325e 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -625,17 +625,32 @@ static inline long sbi_get_firmware_version(void)
long sbi_get_mvendorid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+ static long id = -1;
+
+ if (id < 0)
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+
+ return id;
}
long sbi_get_marchid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+ static long id = -1;
+
+ if (id < 0)
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+
+ return id;
}
long sbi_get_mimpid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+ static long id = -1;
+
+ if (id < 0)
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+
+ return id;
}
static void sbi_send_cpumask_ipi(const struct cpumask *target)
--
2.35.1
next prev parent reply other threads:[~2022-10-04 20:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 20:37 [PATCH v4 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner
2022-10-04 20:37 ` Heiko Stuebner [this message]
2022-10-05 17:07 ` [PATCH 1/2] RISC-V: Cache SBI vendor values Andrew Jones
2022-10-05 23:07 ` Heiko Stuebner
2022-10-04 20:37 ` [PATCH 2/2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner
2022-10-05 17:38 ` Andrew Jones
2022-10-06 19:20 ` Conor Dooley
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