From: Andrew Jones <ajones@ventanamicro.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org,
mark.rutland@arm.com, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Conor.Dooley@microchip.com, cmuellner@linux.com,
samuel@sholland.org
Subject: Re: [PATCH 2/2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
Date: Wed, 5 Oct 2022 19:38:59 +0200 [thread overview]
Message-ID: <20221005173859.apuj4a6iq7fxbffp@kamzik> (raw)
In-Reply-To: <20221004203724.1459763-3-heiko@sntech.de>
On Tue, Oct 04, 2022 at 10:37:24PM +0200, Heiko Stuebner wrote:
> With the T-HEAD C9XX cores being designed before or during the ratification
> to the SSCOFPMF extension, it implements functionality very similar but
> not equal to it.
>
> It implements overflow handling and also some privilege-mode filtering.
> While SSCOFPMF supports this for all modes, the C9XX only implements the
> filtering for M-mode and S-mode but not user-mode.
>
> So add some adaptions to allow the C9XX to still handle
> its PMU through the regular SBI PMU interface instead of defining new
> interfaces or drivers.
>
> To work properly, this requires a matching change in SBI, though the actual
> interface between kernel and SBI does not change.
>
> The main differences are a the overflow CSR and irq number.
>
> As the reading of the overflow-csr is in the hot-path during irq handling,
> use an errata and alternatives to not introduce new conditionals there.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/Kconfig.erratas | 13 +++++++++++
> arch/riscv/errata/thead/errata.c | 18 +++++++++++++++
> arch/riscv/include/asm/errata_list.h | 16 +++++++++++++-
> drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++---------
> 4 files changed, 69 insertions(+), 11 deletions(-)
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2022-10-05 17:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 20:37 [PATCH v4 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner
2022-10-04 20:37 ` [PATCH 1/2] RISC-V: Cache SBI vendor values Heiko Stuebner
2022-10-05 17:07 ` Andrew Jones
2022-10-05 23:07 ` Heiko Stuebner
2022-10-04 20:37 ` [PATCH 2/2] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Heiko Stuebner
2022-10-05 17:38 ` Andrew Jones [this message]
2022-10-06 19:20 ` Conor Dooley
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