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* [PATCH v3 0/4] Add PMEM support for RISC-V
@ 2022-10-19 12:16 Anup Patel
  2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:16 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel

The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.

First two patches are fixes and remaining two patches add the required
PMEM support for Linux RISC-V.

These patches can also be found in riscv_pmem_v3 branch at:
https://github.com/avpatel/linux.git

Changes since v2:
 - Rebased on Linux-6.1-rc1
 - Replaced PATCH1 with the patch proposed by Drew

Changes since v1:
 - Fix error reported by test bot
   https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/

Andrew Jones (1):
  RISC-V: Fix compilation without RISCV_ISA_ZICBOM

Anup Patel (3):
  RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
  RISC-V: Implement arch specific PMEM APIs
  RISC-V: Enable PMEM drivers

 arch/riscv/Kconfig               |  1 +
 arch/riscv/configs/defconfig     |  1 +
 arch/riscv/include/asm/io.h      | 10 ++++++++
 arch/riscv/include/asm/pgtable.h |  2 ++
 arch/riscv/mm/Makefile           |  1 +
 arch/riscv/mm/cacheflush.c       | 41 ++++++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c  | 41 --------------------------------
 arch/riscv/mm/pmem.c             | 21 ++++++++++++++++
 8 files changed, 77 insertions(+), 41 deletions(-)
 create mode 100644 arch/riscv/mm/pmem.c

-- 
2.34.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  2022-10-19 12:16 [PATCH v3 0/4] Add PMEM support for RISC-V Anup Patel
@ 2022-10-19 12:16 ` Anup Patel
  2022-10-19 12:22   ` Anup Patel
  2022-10-19 12:30   ` Heiko Stuebner
  2022-10-19 12:16 ` [PATCH v3 2/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:16 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Andrew Jones, kernel test robot, Anup Patel,
	Conor Dooley

From: Andrew Jones <ajones@ventanamicro.com>

riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
be available and riscv_init_cbom_blocksize() should always be
invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
instructions in the kernel" not "pretend there isn't zicbom, even
when there is". When zicbom is available, whether the kernel enables
its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
Ensure we can build KVM and that the block size is initialized even
when compiling without RISCV_ISA_ZICBOM.

Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/mm/cacheflush.c      | 41 +++++++++++++++++++++++++++++++++
 arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
 2 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..f318b2553612 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -3,6 +3,8 @@
  * Copyright (C) 2017 SiFive
  */
 
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <asm/cacheflush.h>
 
 #ifdef CONFIG_SMP
@@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
 		flush_icache_all();
 }
 #endif /* CONFIG_MMU */
+
+unsigned int riscv_cbom_block_size;
+EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
+
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void)
+{
+	struct device_node *node;
+	unsigned long cbom_hartid;
+	u32 val, probed_block_size;
+	int ret;
+
+	probed_block_size = 0;
+	for_each_of_cpu_node(node) {
+		unsigned long hartid;
+
+		ret = riscv_of_processor_hartid(node, &hartid);
+		if (ret)
+			continue;
+
+		/* set block-size for cbom extension if available */
+		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
+		if (ret)
+			continue;
+
+		if (!probed_block_size) {
+			probed_block_size = val;
+			cbom_hartid = hartid;
+		} else {
+			if (probed_block_size != val)
+				pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
+					cbom_hartid, hartid);
+		}
+	}
+
+	if (probed_block_size)
+		riscv_cbom_block_size = probed_block_size;
+}
+#endif
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index b0add983530a..d919efab6eba 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -8,13 +8,8 @@
 #include <linux/dma-direct.h>
 #include <linux/dma-map-ops.h>
 #include <linux/mm.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
 #include <asm/cacheflush.h>
 
-unsigned int riscv_cbom_block_size;
-EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
-
 static bool noncoherent_supported;
 
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
@@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 	dev->dma_coherent = coherent;
 }
 
-#ifdef CONFIG_RISCV_ISA_ZICBOM
-void riscv_init_cbom_blocksize(void)
-{
-	struct device_node *node;
-	unsigned long cbom_hartid;
-	u32 val, probed_block_size;
-	int ret;
-
-	probed_block_size = 0;
-	for_each_of_cpu_node(node) {
-		unsigned long hartid;
-
-		ret = riscv_of_processor_hartid(node, &hartid);
-		if (ret)
-			continue;
-
-		/* set block-size for cbom extension if available */
-		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
-		if (ret)
-			continue;
-
-		if (!probed_block_size) {
-			probed_block_size = val;
-			cbom_hartid = hartid;
-		} else {
-			if (probed_block_size != val)
-				pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
-					cbom_hartid, hartid);
-		}
-	}
-
-	if (probed_block_size)
-		riscv_cbom_block_size = probed_block_size;
-}
-#endif
-
 void riscv_noncoherent_supported(void)
 {
 	WARN(!riscv_cbom_block_size,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v3 2/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
  2022-10-19 12:16 [PATCH v3 0/4] Add PMEM support for RISC-V Anup Patel
  2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
@ 2022-10-19 12:16 ` Anup Patel
  2022-10-19 12:16 ` [PATCH v3 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
  2022-10-19 12:16 ` [PATCH v3 4/4] RISC-V: Enable PMEM drivers Anup Patel
  3 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:16 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

Currently, all flavors of ioremap_xyz() function maps to the generic
ioremap() which means any ioremap_xyz() call will always map the
target memory as IO using _PAGE_IOREMAP page attributes. This breaks
ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory
remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP
page attributes.

To address above (just like other architectures), we implement RISC-V
specific ioremap_cache() and ioremap_wc() which maps memory using page
attributes as defined by the Svpbmt specification.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/io.h      | 10 ++++++++++
 arch/riscv/include/asm/pgtable.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 92080a227937..92a31e543388 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size)		\
+	ioremap_prot((addr), (size), _PAGE_IOREMAP_WC)
+#endif
+
 #include <asm-generic/io.h>
 
+#ifdef CONFIG_MMU
+#define ioremap_cache(addr, size)	\
+	ioremap_prot((addr), (size), _PAGE_KERNEL)
+#endif
+
 #endif /* _ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7ec936910a96..346b7c1a3eeb 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata;
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 
 #define _PAGE_IOREMAP	((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
+#define _PAGE_IOREMAP_WC	((_PAGE_KERNEL & ~_PAGE_MTMASK) | \
+				 _PAGE_NOCACHE)
 #define PAGE_KERNEL_IO		__pgprot(_PAGE_IOREMAP)
 
 extern pgd_t swapper_pg_dir[];
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v3 3/4] RISC-V: Implement arch specific PMEM APIs
  2022-10-19 12:16 [PATCH v3 0/4] Add PMEM support for RISC-V Anup Patel
  2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
  2022-10-19 12:16 ` [PATCH v3 2/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel
@ 2022-10-19 12:16 ` Anup Patel
  2022-10-19 12:16 ` [PATCH v3 4/4] RISC-V: Enable PMEM drivers Anup Patel
  3 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:16 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel, Mayuresh Chitale

The NVDIMM PMEM driver expects arch specific APIs for cache maintenance
and if arch does not provide these APIs then NVDIMM PMEM driver will
always use MEMREMAP_WT to map persistent memory which in-turn maps as
UC memory type defined by the RISC-V Svpbmt specification.

Now that the Svpbmt and Zicbom support is available in RISC-V kernel,
we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM
PMEM driver can use MEMREMAP_WB to map persistent memory.

Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/Kconfig     |  1 +
 arch/riscv/mm/Makefile |  1 +
 arch/riscv/mm/pmem.c   | 21 +++++++++++++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/mm/pmem.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6b48a3ae9843..025e2a1b1c60 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,6 +25,7 @@ config RISCV
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
 	select ARCH_HAS_MMIOWB
+	select ARCH_HAS_PMEM_API
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP if MMU
 	select ARCH_HAS_SET_MEMORY if MMU
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index d76aabf4b94d..3b368e547f83 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -31,3 +31,4 @@ endif
 
 obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
 obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
+obj-$(CONFIG_ARCH_HAS_PMEM_API) += pmem.o
diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c
new file mode 100644
index 000000000000..089df92ae876
--- /dev/null
+++ b/arch/riscv/mm/pmem.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/export.h>
+#include <linux/libnvdimm.h>
+
+#include <asm/cacheflush.h>
+
+void arch_wb_cache_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
+
+void arch_invalidate_pmem(void *addr, size_t size)
+{
+	ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
+}
+EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v3 4/4] RISC-V: Enable PMEM drivers
  2022-10-19 12:16 [PATCH v3 0/4] Add PMEM support for RISC-V Anup Patel
                   ` (2 preceding siblings ...)
  2022-10-19 12:16 ` [PATCH v3 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
@ 2022-10-19 12:16 ` Anup Patel
  3 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:16 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, linux-riscv,
	linux-kernel, Anup Patel

We now have PMEM arch support available in RISC-V kernel so let us
enable relevant drivers in defconfig.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..462da9f7410d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_RPMSG_CHAR=y
 CONFIG_RPMSG_CTRL=y
 CONFIG_RPMSG_VIRTIO=y
+CONFIG_LIBNVDIMM=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
@ 2022-10-19 12:22   ` Anup Patel
  2022-10-19 12:30   ` Heiko Stuebner
  1 sibling, 0 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:22 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: Paul Walmsley, Atish Patra, Heiko Stuebner, linux-riscv,
	linux-kernel, Andrew Jones, kernel test robot, Anup Patel,
	Conor Dooley

Hi Palmer,

On Wed, Oct 19, 2022 at 5:46 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> From: Andrew Jones <ajones@ventanamicro.com>
>
> riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
> be available and riscv_init_cbom_blocksize() should always be
> invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
> is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
> instructions in the kernel" not "pretend there isn't zicbom, even
> when there is". When zicbom is available, whether the kernel enables
> its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
> Ensure we can build KVM and that the block size is initialized even
> when compiling without RISCV_ISA_ZICBOM.
>
> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Currently, the KVM RISC-V compilation is broken for toolchains not
having Zicbom support.

I plan to take this patch through the KVM RISC-V tree and I will be
sending a PR by the end of this week. Let me know if you want this
patch to go through the RISC-V tree.

Regards,
Anup

> ---
>  arch/riscv/mm/cacheflush.c      | 41 +++++++++++++++++++++++++++++++++
>  arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
>  2 files changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 6cb7d96ad9c7..f318b2553612 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -3,6 +3,8 @@
>   * Copyright (C) 2017 SiFive
>   */
>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <asm/cacheflush.h>
>
>  #ifdef CONFIG_SMP
> @@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
>                 flush_icache_all();
>  }
>  #endif /* CONFIG_MMU */
> +
> +unsigned int riscv_cbom_block_size;
> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> +
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +void riscv_init_cbom_blocksize(void)
> +{
> +       struct device_node *node;
> +       unsigned long cbom_hartid;
> +       u32 val, probed_block_size;
> +       int ret;
> +
> +       probed_block_size = 0;
> +       for_each_of_cpu_node(node) {
> +               unsigned long hartid;
> +
> +               ret = riscv_of_processor_hartid(node, &hartid);
> +               if (ret)
> +                       continue;
> +
> +               /* set block-size for cbom extension if available */
> +               ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> +               if (ret)
> +                       continue;
> +
> +               if (!probed_block_size) {
> +                       probed_block_size = val;
> +                       cbom_hartid = hartid;
> +               } else {
> +                       if (probed_block_size != val)
> +                               pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> +                                       cbom_hartid, hartid);
> +               }
> +       }
> +
> +       if (probed_block_size)
> +               riscv_cbom_block_size = probed_block_size;
> +}
> +#endif
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index b0add983530a..d919efab6eba 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -8,13 +8,8 @@
>  #include <linux/dma-direct.h>
>  #include <linux/dma-map-ops.h>
>  #include <linux/mm.h>
> -#include <linux/of.h>
> -#include <linux/of_device.h>
>  #include <asm/cacheflush.h>
>
> -unsigned int riscv_cbom_block_size;
> -EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> -
>  static bool noncoherent_supported;
>
>  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
>         dev->dma_coherent = coherent;
>  }
>
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -void riscv_init_cbom_blocksize(void)
> -{
> -       struct device_node *node;
> -       unsigned long cbom_hartid;
> -       u32 val, probed_block_size;
> -       int ret;
> -
> -       probed_block_size = 0;
> -       for_each_of_cpu_node(node) {
> -               unsigned long hartid;
> -
> -               ret = riscv_of_processor_hartid(node, &hartid);
> -               if (ret)
> -                       continue;
> -
> -               /* set block-size for cbom extension if available */
> -               ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> -               if (ret)
> -                       continue;
> -
> -               if (!probed_block_size) {
> -                       probed_block_size = val;
> -                       cbom_hartid = hartid;
> -               } else {
> -                       if (probed_block_size != val)
> -                               pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> -                                       cbom_hartid, hartid);
> -               }
> -       }
> -
> -       if (probed_block_size)
> -               riscv_cbom_block_size = probed_block_size;
> -}
> -#endif
> -
>  void riscv_noncoherent_supported(void)
>  {
>         WARN(!riscv_cbom_block_size,
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
  2022-10-19 12:22   ` Anup Patel
@ 2022-10-19 12:30   ` Heiko Stuebner
  2022-10-19 12:35     ` Conor.Dooley
  2022-10-19 12:36     ` Anup Patel
  1 sibling, 2 replies; 9+ messages in thread
From: Heiko Stuebner @ 2022-10-19 12:30 UTC (permalink / raw)
  To: Palmer Dabbelt, Paul Walmsley, Anup Patel
  Cc: Atish Patra, Anup Patel, linux-riscv, linux-kernel, Andrew Jones,
	kernel test robot, Anup Patel, Conor Dooley

Hi Anup,

Am Mittwoch, 19. Oktober 2022, 14:16:19 CEST schrieb Anup Patel:
> From: Andrew Jones <ajones@ventanamicro.com>
> 
> riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
> be available and riscv_init_cbom_blocksize() should always be
> invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
> is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
> instructions in the kernel" not "pretend there isn't zicbom, even
> when there is". When zicbom is available, whether the kernel enables
> its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
> Ensure we can build KVM and that the block size is initialized even
> when compiling without RISCV_ISA_ZICBOM.

either I'm way very low on coffee or something is strange here :-) .

I can fully grasp the need to init the cbom blocksize for guests, even when
the main kernel isn't using it, but below in the patch itself it is still:

+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void)
+{
[...]

so the init_cbom_blocksize function is still inside a RISCV_ISA_ZICBOM
ifdef?


Heiko


> 
> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/mm/cacheflush.c      | 41 +++++++++++++++++++++++++++++++++
>  arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
>  2 files changed, 41 insertions(+), 41 deletions(-)
> 
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 6cb7d96ad9c7..f318b2553612 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -3,6 +3,8 @@
>   * Copyright (C) 2017 SiFive
>   */
>  
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <asm/cacheflush.h>
>  
>  #ifdef CONFIG_SMP
> @@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
>  		flush_icache_all();
>  }
>  #endif /* CONFIG_MMU */
> +
> +unsigned int riscv_cbom_block_size;
> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> +
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +void riscv_init_cbom_blocksize(void)
> +{
> +	struct device_node *node;
> +	unsigned long cbom_hartid;
> +	u32 val, probed_block_size;
> +	int ret;
> +
> +	probed_block_size = 0;
> +	for_each_of_cpu_node(node) {
> +		unsigned long hartid;
> +
> +		ret = riscv_of_processor_hartid(node, &hartid);
> +		if (ret)
> +			continue;
> +
> +		/* set block-size for cbom extension if available */
> +		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> +		if (ret)
> +			continue;
> +
> +		if (!probed_block_size) {
> +			probed_block_size = val;
> +			cbom_hartid = hartid;
> +		} else {
> +			if (probed_block_size != val)
> +				pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> +					cbom_hartid, hartid);
> +		}
> +	}
> +
> +	if (probed_block_size)
> +		riscv_cbom_block_size = probed_block_size;
> +}
> +#endif
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index b0add983530a..d919efab6eba 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -8,13 +8,8 @@
>  #include <linux/dma-direct.h>
>  #include <linux/dma-map-ops.h>
>  #include <linux/mm.h>
> -#include <linux/of.h>
> -#include <linux/of_device.h>
>  #include <asm/cacheflush.h>
>  
> -unsigned int riscv_cbom_block_size;
> -EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> -
>  static bool noncoherent_supported;
>  
>  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
>  	dev->dma_coherent = coherent;
>  }
>  
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -void riscv_init_cbom_blocksize(void)
> -{
> -	struct device_node *node;
> -	unsigned long cbom_hartid;
> -	u32 val, probed_block_size;
> -	int ret;
> -
> -	probed_block_size = 0;
> -	for_each_of_cpu_node(node) {
> -		unsigned long hartid;
> -
> -		ret = riscv_of_processor_hartid(node, &hartid);
> -		if (ret)
> -			continue;
> -
> -		/* set block-size for cbom extension if available */
> -		ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> -		if (ret)
> -			continue;
> -
> -		if (!probed_block_size) {
> -			probed_block_size = val;
> -			cbom_hartid = hartid;
> -		} else {
> -			if (probed_block_size != val)
> -				pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> -					cbom_hartid, hartid);
> -		}
> -	}
> -
> -	if (probed_block_size)
> -		riscv_cbom_block_size = probed_block_size;
> -}
> -#endif
> -
>  void riscv_noncoherent_supported(void)
>  {
>  	WARN(!riscv_cbom_block_size,
> 





^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  2022-10-19 12:30   ` Heiko Stuebner
@ 2022-10-19 12:35     ` Conor.Dooley
  2022-10-19 12:36     ` Anup Patel
  1 sibling, 0 replies; 9+ messages in thread
From: Conor.Dooley @ 2022-10-19 12:35 UTC (permalink / raw)
  To: heiko, palmer, paul.walmsley, apatel
  Cc: atishp, anup, linux-riscv, linux-kernel, ajones, lkp

On 19/10/2022 13:30, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Anup,
> 
> Am Mittwoch, 19. Oktober 2022, 14:16:19 CEST schrieb Anup Patel:
>> From: Andrew Jones <ajones@ventanamicro.com>
>>
>> riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
>> be available and riscv_init_cbom_blocksize() should always be
>> invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
>> is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
>> instructions in the kernel" not "pretend there isn't zicbom, even
>> when there is". When zicbom is available, whether the kernel enables
>> its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
>> Ensure we can build KVM and that the block size is initialized even
>> when compiling without RISCV_ISA_ZICBOM.
> 
> either I'm way very low on coffee or something is strange here :-) .
> 
> I can fully grasp the need to init the cbom blocksize for guests, even when
> the main kernel isn't using it, but below in the patch itself it is still:
> 
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +void riscv_init_cbom_blocksize(void)
> +{
> [...]
> 
> so the init_cbom_blocksize function is still inside a RISCV_ISA_ZICBOM
> ifdef?

FWIW:
Drew's patch, or at least the version of it that I have been using/did
a review of, does not have init_cbom_blocksize() inside such a #ifdef.

> 
> 
> Heiko
> 
> 
>>
>> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
>> Reported-by: kernel test robot <lkp@intel.com>
>> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>>   arch/riscv/mm/cacheflush.c      | 41 +++++++++++++++++++++++++++++++++
>>   arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
>>   2 files changed, 41 insertions(+), 41 deletions(-)
>>
>> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
>> index 6cb7d96ad9c7..f318b2553612 100644
>> --- a/arch/riscv/mm/cacheflush.c
>> +++ b/arch/riscv/mm/cacheflush.c
>> @@ -3,6 +3,8 @@
>>    * Copyright (C) 2017 SiFive
>>    */
>>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>>   #include <asm/cacheflush.h>
>>
>>   #ifdef CONFIG_SMP
>> @@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
>>                flush_icache_all();
>>   }
>>   #endif /* CONFIG_MMU */
>> +
>> +unsigned int riscv_cbom_block_size;
>> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
>> +
>> +#ifdef CONFIG_RISCV_ISA_ZICBOM
>> +void riscv_init_cbom_blocksize(void)
>> +{
>> +     struct device_node *node;
>> +     unsigned long cbom_hartid;
>> +     u32 val, probed_block_size;
>> +     int ret;
>> +
>> +     probed_block_size = 0;
>> +     for_each_of_cpu_node(node) {
>> +             unsigned long hartid;
>> +
>> +             ret = riscv_of_processor_hartid(node, &hartid);
>> +             if (ret)
>> +                     continue;
>> +
>> +             /* set block-size for cbom extension if available */
>> +             ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
>> +             if (ret)
>> +                     continue;
>> +
>> +             if (!probed_block_size) {
>> +                     probed_block_size = val;
>> +                     cbom_hartid = hartid;
>> +             } else {
>> +                     if (probed_block_size != val)
>> +                             pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
>> +                                     cbom_hartid, hartid);
>> +             }
>> +     }
>> +
>> +     if (probed_block_size)
>> +             riscv_cbom_block_size = probed_block_size;
>> +}
>> +#endif
>> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
>> index b0add983530a..d919efab6eba 100644
>> --- a/arch/riscv/mm/dma-noncoherent.c
>> +++ b/arch/riscv/mm/dma-noncoherent.c
>> @@ -8,13 +8,8 @@
>>   #include <linux/dma-direct.h>
>>   #include <linux/dma-map-ops.h>
>>   #include <linux/mm.h>
>> -#include <linux/of.h>
>> -#include <linux/of_device.h>
>>   #include <asm/cacheflush.h>
>>
>> -unsigned int riscv_cbom_block_size;
>> -EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
>> -
>>   static bool noncoherent_supported;
>>
>>   void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
>> @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
>>        dev->dma_coherent = coherent;
>>   }
>>
>> -#ifdef CONFIG_RISCV_ISA_ZICBOM
>> -void riscv_init_cbom_blocksize(void)
>> -{
>> -     struct device_node *node;
>> -     unsigned long cbom_hartid;
>> -     u32 val, probed_block_size;
>> -     int ret;
>> -
>> -     probed_block_size = 0;
>> -     for_each_of_cpu_node(node) {
>> -             unsigned long hartid;
>> -
>> -             ret = riscv_of_processor_hartid(node, &hartid);
>> -             if (ret)
>> -                     continue;
>> -
>> -             /* set block-size for cbom extension if available */
>> -             ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
>> -             if (ret)
>> -                     continue;
>> -
>> -             if (!probed_block_size) {
>> -                     probed_block_size = val;
>> -                     cbom_hartid = hartid;
>> -             } else {
>> -                     if (probed_block_size != val)
>> -                             pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
>> -                                     cbom_hartid, hartid);
>> -             }
>> -     }
>> -
>> -     if (probed_block_size)
>> -             riscv_cbom_block_size = probed_block_size;
>> -}
>> -#endif
>> -
>>   void riscv_noncoherent_supported(void)
>>   {
>>        WARN(!riscv_cbom_block_size,
>>
> 
> 
> 
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  2022-10-19 12:30   ` Heiko Stuebner
  2022-10-19 12:35     ` Conor.Dooley
@ 2022-10-19 12:36     ` Anup Patel
  1 sibling, 0 replies; 9+ messages in thread
From: Anup Patel @ 2022-10-19 12:36 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Palmer Dabbelt, Paul Walmsley, Atish Patra, Anup Patel,
	linux-riscv, linux-kernel, Andrew Jones, kernel test robot,
	Conor Dooley

On Wed, Oct 19, 2022 at 6:01 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Hi Anup,
>
> Am Mittwoch, 19. Oktober 2022, 14:16:19 CEST schrieb Anup Patel:
> > From: Andrew Jones <ajones@ventanamicro.com>
> >
> > riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
> > be available and riscv_init_cbom_blocksize() should always be
> > invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
> > is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
> > instructions in the kernel" not "pretend there isn't zicbom, even
> > when there is". When zicbom is available, whether the kernel enables
> > its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
> > Ensure we can build KVM and that the block size is initialized even
> > when compiling without RISCV_ISA_ZICBOM.
>
> either I'm way very low on coffee or something is strange here :-) .
>
> I can fully grasp the need to init the cbom blocksize for guests, even when
> the main kernel isn't using it, but below in the patch itself it is still:

The Guest might have pass-through access to a device which is not
cache-coherent whereas Host might have all devices cache-coherent.

>
> +#ifdef CONFIG_RISCV_ISA_ZICBOM
> +void riscv_init_cbom_blocksize(void)
> +{
> [...]
>
> so the init_cbom_blocksize function is still inside a RISCV_ISA_ZICBOM
> ifdef?

Argh, I mixed changes from my previous patch and Drew's patch.

I will quickly send v4. Thanks for catching.

Regards,
Anup

>
>
> Heiko
>
>
> >
> > Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing")
> > Reported-by: kernel test robot <lkp@intel.com>
> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  arch/riscv/mm/cacheflush.c      | 41 +++++++++++++++++++++++++++++++++
> >  arch/riscv/mm/dma-noncoherent.c | 41 ---------------------------------
> >  2 files changed, 41 insertions(+), 41 deletions(-)
> >
> > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> > index 6cb7d96ad9c7..f318b2553612 100644
> > --- a/arch/riscv/mm/cacheflush.c
> > +++ b/arch/riscv/mm/cacheflush.c
> > @@ -3,6 +3,8 @@
> >   * Copyright (C) 2017 SiFive
> >   */
> >
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> >  #include <asm/cacheflush.h>
> >
> >  #ifdef CONFIG_SMP
> > @@ -86,3 +88,42 @@ void flush_icache_pte(pte_t pte)
> >               flush_icache_all();
> >  }
> >  #endif /* CONFIG_MMU */
> > +
> > +unsigned int riscv_cbom_block_size;
> > +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> > +
> > +#ifdef CONFIG_RISCV_ISA_ZICBOM
> > +void riscv_init_cbom_blocksize(void)
> > +{
> > +     struct device_node *node;
> > +     unsigned long cbom_hartid;
> > +     u32 val, probed_block_size;
> > +     int ret;
> > +
> > +     probed_block_size = 0;
> > +     for_each_of_cpu_node(node) {
> > +             unsigned long hartid;
> > +
> > +             ret = riscv_of_processor_hartid(node, &hartid);
> > +             if (ret)
> > +                     continue;
> > +
> > +             /* set block-size for cbom extension if available */
> > +             ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> > +             if (ret)
> > +                     continue;
> > +
> > +             if (!probed_block_size) {
> > +                     probed_block_size = val;
> > +                     cbom_hartid = hartid;
> > +             } else {
> > +                     if (probed_block_size != val)
> > +                             pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> > +                                     cbom_hartid, hartid);
> > +             }
> > +     }
> > +
> > +     if (probed_block_size)
> > +             riscv_cbom_block_size = probed_block_size;
> > +}
> > +#endif
> > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > index b0add983530a..d919efab6eba 100644
> > --- a/arch/riscv/mm/dma-noncoherent.c
> > +++ b/arch/riscv/mm/dma-noncoherent.c
> > @@ -8,13 +8,8 @@
> >  #include <linux/dma-direct.h>
> >  #include <linux/dma-map-ops.h>
> >  #include <linux/mm.h>
> > -#include <linux/of.h>
> > -#include <linux/of_device.h>
> >  #include <asm/cacheflush.h>
> >
> > -unsigned int riscv_cbom_block_size;
> > -EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
> > -
> >  static bool noncoherent_supported;
> >
> >  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> > @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> >       dev->dma_coherent = coherent;
> >  }
> >
> > -#ifdef CONFIG_RISCV_ISA_ZICBOM
> > -void riscv_init_cbom_blocksize(void)
> > -{
> > -     struct device_node *node;
> > -     unsigned long cbom_hartid;
> > -     u32 val, probed_block_size;
> > -     int ret;
> > -
> > -     probed_block_size = 0;
> > -     for_each_of_cpu_node(node) {
> > -             unsigned long hartid;
> > -
> > -             ret = riscv_of_processor_hartid(node, &hartid);
> > -             if (ret)
> > -                     continue;
> > -
> > -             /* set block-size for cbom extension if available */
> > -             ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
> > -             if (ret)
> > -                     continue;
> > -
> > -             if (!probed_block_size) {
> > -                     probed_block_size = val;
> > -                     cbom_hartid = hartid;
> > -             } else {
> > -                     if (probed_block_size != val)
> > -                             pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
> > -                                     cbom_hartid, hartid);
> > -             }
> > -     }
> > -
> > -     if (probed_block_size)
> > -             riscv_cbom_block_size = probed_block_size;
> > -}
> > -#endif
> > -
> >  void riscv_noncoherent_supported(void)
> >  {
> >       WARN(!riscv_cbom_block_size,
> >
>
>
>
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-10-19 13:06 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-19 12:16 [PATCH v3 0/4] Add PMEM support for RISC-V Anup Patel
2022-10-19 12:16 ` [PATCH v3 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
2022-10-19 12:22   ` Anup Patel
2022-10-19 12:30   ` Heiko Stuebner
2022-10-19 12:35     ` Conor.Dooley
2022-10-19 12:36     ` Anup Patel
2022-10-19 12:16 ` [PATCH v3 2/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel
2022-10-19 12:16 ` [PATCH v3 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
2022-10-19 12:16 ` [PATCH v3 4/4] RISC-V: Enable PMEM drivers Anup Patel

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