From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
marpagan@redhat.com
Cc: Matthew Gerlach <matthew.gerlach@intel.com>
Subject: [PATCH v4 0/4] Enhance definition of DFH and use enhancements for uart driver
Date: Thu, 20 Oct 2022 14:26:06 -0700 [thread overview]
Message-ID: <20221020212610.697729-1-matthew.gerlach@linux.intel.com> (raw)
From: Matthew Gerlach <matthew.gerlach@intel.com>
This patchset enhances the definition of the Device Feature Header (DFH) used by
the Device Feature List (DFL) bus and then uses the new enhancements in a uart
driver.
Patch 1 updates the DFL documentation to provide the motivation behind the
enhancements to the definition of the DFH.
Patch 2 adds the definitions for DFHv1.
Patch 3 adds basic support DFHv1. It provides a generic mechanism for
describing MSIX interrupts used by a particular feature instance, and
it gets the location and size of the feature's register set from DFHv1.
Patch 4 adds a DFL uart driver that makes use of the new features of DFHv1.
Basheer Ahmed Muddebihal (1):
fpga: dfl: Add DFHv1 Register Definitions
Matthew Gerlach (3):
Documentation: fpga: dfl: Add documentation for DFHv1
fpga: dfl: add basic support DFHv1
tty: serial: 8250: add DFL bus driver for Altera 16550.
Documentation/fpga/dfl.rst | 96 ++++++++++++
drivers/fpga/dfl.c | 234 +++++++++++++++++++++++------
drivers/fpga/dfl.h | 38 +++++
drivers/tty/serial/8250/8250_dfl.c | 149 ++++++++++++++++++
drivers/tty/serial/8250/Kconfig | 12 ++
drivers/tty/serial/8250/Makefile | 1 +
include/linux/dfl.h | 15 ++
7 files changed, 496 insertions(+), 49 deletions(-)
create mode 100644 drivers/tty/serial/8250/8250_dfl.c
--
2.25.1
next reply other threads:[~2022-10-20 21:26 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 21:26 matthew.gerlach [this message]
2022-10-20 21:26 ` [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-21 3:55 ` Bagas Sanjaya
2022-10-24 15:01 ` matthew.gerlach
2022-10-21 8:28 ` Ilpo Järvinen
2022-10-21 8:36 ` Ilpo Järvinen
2022-10-20 21:26 ` [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-21 8:06 ` Ilpo Järvinen
2022-10-24 15:03 ` matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 3/4] fpga: dfl: add basic support DFHv1 matthew.gerlach
2022-10-20 22:07 ` Andy Shevchenko
2022-10-24 14:56 ` matthew.gerlach
2022-10-21 8:58 ` Ilpo Järvinen
2022-10-24 15:09 ` matthew.gerlach
2022-10-21 9:07 ` Ilpo Järvinen
2022-10-29 13:08 ` Xu Yilun
2022-10-29 14:47 ` matthew.gerlach
2022-11-01 22:37 ` matthew.gerlach
2022-11-03 1:36 ` Xu Yilun
2022-10-30 22:06 ` Andy Shevchenko
2022-10-31 1:16 ` Xu Yilun
2022-10-31 15:34 ` Andy Shevchenko
2022-10-31 20:15 ` matthew.gerlach
2022-11-01 1:55 ` Xu Yilun
2022-10-20 21:26 ` [PATCH v4 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-20 22:13 ` Andy Shevchenko
2022-10-21 4:33 ` Greg KH
2022-10-21 9:24 ` Ilpo Järvinen
2022-10-29 15:24 ` Xu Yilun
2022-11-01 0:34 ` matthew.gerlach
2022-11-01 1:46 ` Xu Yilun
2022-11-01 16:04 ` matthew.gerlach
2022-11-01 16:30 ` Ilpo Järvinen
2022-11-01 17:39 ` matthew.gerlach
2022-11-02 9:57 ` Ilpo Järvinen
2022-11-08 12:48 ` Marco Pagani
2022-11-08 12:51 ` Ilpo Järvinen
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