From: Xu Yilun <yilun.xu@intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net, jirislaby@kernel.org,
geert+renesas@glider.be, andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
marpagan@redhat.com
Subject: Re: [PATCH v4 3/4] fpga: dfl: add basic support DFHv1
Date: Thu, 3 Nov 2022 09:36:33 +0800 [thread overview]
Message-ID: <Y2MbIV5lJBgIsA4D@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <alpine.DEB.2.22.394.2211011520290.2767909@rhweight-WRK1>
On 2022-11-01 at 15:37:19 -0700, matthew.gerlach@linux.intel.com wrote:
>
>
> On Sat, 29 Oct 2022, matthew.gerlach@linux.intel.com wrote:
>
> >
> > >
> > > > if (!finfo)
> > > > return -ENOMEM;
> > > >
> > > > + if (dfh_psize > 0) {
> > > > + memcpy_fromio(finfo->params,
> > > > + binfo->ioaddr + ofst + DFHv1_PARAM_HDR, dfh_psize);
> > > > + finfo->param_size = dfh_psize;
> > > > + }
> > > > +
> > > > finfo->fid = fid;
> > > > finfo->revision = revision;
> > > > - finfo->mmio_res.start = binfo->start + ofst;
> > > > - finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
> > > > + finfo->dfh_version = dfh_ver;
> > > > finfo->mmio_res.flags = IORESOURCE_MEM;
> > > > - finfo->irq_base = irq_base;
> > > > - finfo->nr_irqs = nr_irqs;
> > > > + if (dfh_ver == 1) {
> > > > + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR);
> > > > + if (v & DFHv1_CSR_ADDR_REL)
> > > > + finfo->mmio_res.start = v & ~DFHv1_CSR_ADDR_REL;
> > > > + else
> > > > + finfo->mmio_res.start = binfo->start + ofst +
> > > > + FIELD_GET(DFHv1_CSR_ADDR_MASK, v);
> > > > +
> > > > + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP);
> > > > + finfo->mmio_res.end = finfo->mmio_res.start +
> > > > + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1;
> > >
> > > So for dflv1, no feature header resource for dfl_device, is it a problem
> > > for dfl_uio? Does userspace driver need the raw feature header?
> > These are two very good questions. The dfl_uio driver question is
> > particularly relevent because user space is looking at the GUIDs.
> >
>
> In the case of dfl_uio driver, user space will definitely want to look at
> the feature header for the GUID and the parameters. Since DFHv1 can have
> the DFH header and the feature registers in non-contiguous memory locations,
> a resource for the dfl_device will be required. In earlier
> revisions of this patch set, a second resource was added called csr_res
> pointing to the feature's register while mmio_res pointed at the header.
> Do we just need better names or do we need an array of named resources?
Either is OK, you could also name a resource element in an array by
struct resource:name. But my concern is still no overlapping.
Thanks,
Yilun
next prev parent reply other threads:[~2022-11-03 1:45 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 21:26 [PATCH v4 0/4] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-10-21 3:55 ` Bagas Sanjaya
2022-10-24 15:01 ` matthew.gerlach
2022-10-21 8:28 ` Ilpo Järvinen
2022-10-21 8:36 ` Ilpo Järvinen
2022-10-20 21:26 ` [PATCH v4 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-10-21 8:06 ` Ilpo Järvinen
2022-10-24 15:03 ` matthew.gerlach
2022-10-20 21:26 ` [PATCH v4 3/4] fpga: dfl: add basic support DFHv1 matthew.gerlach
2022-10-20 22:07 ` Andy Shevchenko
2022-10-24 14:56 ` matthew.gerlach
2022-10-21 8:58 ` Ilpo Järvinen
2022-10-24 15:09 ` matthew.gerlach
2022-10-21 9:07 ` Ilpo Järvinen
2022-10-29 13:08 ` Xu Yilun
2022-10-29 14:47 ` matthew.gerlach
2022-11-01 22:37 ` matthew.gerlach
2022-11-03 1:36 ` Xu Yilun [this message]
2022-10-30 22:06 ` Andy Shevchenko
2022-10-31 1:16 ` Xu Yilun
2022-10-31 15:34 ` Andy Shevchenko
2022-10-31 20:15 ` matthew.gerlach
2022-11-01 1:55 ` Xu Yilun
2022-10-20 21:26 ` [PATCH v4 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-10-20 22:13 ` Andy Shevchenko
2022-10-21 4:33 ` Greg KH
2022-10-21 9:24 ` Ilpo Järvinen
2022-10-29 15:24 ` Xu Yilun
2022-11-01 0:34 ` matthew.gerlach
2022-11-01 1:46 ` Xu Yilun
2022-11-01 16:04 ` matthew.gerlach
2022-11-01 16:30 ` Ilpo Järvinen
2022-11-01 17:39 ` matthew.gerlach
2022-11-02 9:57 ` Ilpo Järvinen
2022-11-08 12:48 ` Marco Pagani
2022-11-08 12:51 ` Ilpo Järvinen
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