* [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper
@ 2022-10-21 17:18 Rahul T R
2022-10-21 17:18 ` [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml Rahul T R
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v8:
- Rebased to 6.1-rc1
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112 ----
.../bindings/display/bridge/cdns,dsi.yaml | 180 +++++++
drivers/gpu/drm/bridge/Kconfig | 11 -
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig | 21 +
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 483 ++----------------
.../gpu/drm/bridge/cadence/cdns-dsi-core.h | 471 +++++++++++++++++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 ++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +
10 files changed, 781 insertions(+), 570 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (65%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.38.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
@ 2022-10-21 17:18 ` Rahul T R
2022-10-21 17:18 ` [PATCH v8 2/5] dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on j721e Rahul T R
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R, Rob Herring
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -------------
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++++++++++++++++++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==================
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c0000 {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c0000 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "<vendor,panel>";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c0000 {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c0000 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "<vendor,panel>";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output>;
- };
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
new file mode 100644
index 000000000000..3161c33093c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DSI bridge
+
+maintainers:
+ - Boris Brezillon <boris.brezillon@bootlin.com>
+
+description: |
+ CDNS DSI is a bridge device which converts DPI to DSI
+
+properties:
+ compatible:
+ enum:
+ - cdns,dsi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PSM clock, used by the IP
+ - description: sys clock, used by the IP
+
+ clock-names:
+ items:
+ - const: dsi_p_clk
+ - const: dsi_sys_clk
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: dphy
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: dsi_p_rst
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port representing the DSI output. It can have
+ at most 4 endpoints. The endpoint number is directly encoding
+ the DSI virtual channel used by this device.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port representing the DPI input.
+
+ required:
+ - port@1
+
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi@fd0c0000 {
+ compatible = "cdns,dsi";
+ reg = <0x0 0xfd0c0000 0x0 0x1000>;
+ clocks = <&pclk>, <&sysclk>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ interrupts = <1>;
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&xxx_dpi_output>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "panasonic,vvx10f034n00";
+ reg = <0>;
+ power-supply = <&vcc_lcd_reg>;
+ };
+ };
+ };
+
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi@fd0c0000 {
+ compatible = "cdns,dsi";
+ reg = <0x0 0xfd0c0000 0x0 0x1000>;
+ clocks = <&pclk>, <&sysclk>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ interrupts = <1>;
+ phys = <&dphy1>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_panel_input>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&xxx_dpi_output>;
+ };
+ };
+ };
+ };
+ };
--
2.38.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 2/5] dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on j721e
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
2022-10-21 17:18 ` [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml Rahul T R
@ 2022-10-21 17:18 ` Rahul T R
2022-10-21 17:18 ` [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence Rahul T R
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R, Rob Herring
Add compatible to support dsi bridge on j721e
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/bridge/cdns,dsi.yaml | 25 ++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
index 3161c33093c1..23060324d16e 100644
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
@@ -16,9 +16,15 @@ properties:
compatible:
enum:
- cdns,dsi
+ - ti,j721e-dsi
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description:
+ Register block for controller's registers.
+ - description:
+ Register block for wrapper settings registers in case of TI J7 SoCs.
clocks:
items:
@@ -67,6 +73,23 @@ properties:
allOf:
- $ref: ../dsi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j721e-dsi
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ power-domains:
+ maxItems: 1
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.38.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
2022-10-21 17:18 ` [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml Rahul T R
2022-10-21 17:18 ` [PATCH v8 2/5] dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on j721e Rahul T R
@ 2022-10-21 17:18 ` Rahul T R
2022-10-26 6:15 ` Tomi Valkeinen
2022-10-21 17:18 ` [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file Rahul T R
2022-10-21 17:18 ` [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper Rahul T R
4 siblings, 1 reply; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
drivers/gpu/drm/bridge/Kconfig | 11 -----------
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig | 11 +++++++++++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} | 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..8fbb46c66094 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..e3d8e9a40784 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,5 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.38.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
` (2 preceding siblings ...)
2022-10-21 17:18 ` [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence Rahul T R
@ 2022-10-21 17:18 ` Rahul T R
2022-10-26 6:16 ` Tomi Valkeinen
2022-10-21 17:18 ` [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper Rahul T R
4 siblings, 1 reply; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R
Create a header file for cdns dsi and move
register offsets and structure to header,
to prepare for adding j721e wrapper support
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
.../gpu/drm/bridge/cadence/cdns-dsi-core.c | 446 +----------------
.../gpu/drm/bridge/cadence/cdns-dsi-core.h | 458 ++++++++++++++++++
2 files changed, 459 insertions(+), 445 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index 20bece84ff8c..cba91247ab26 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -6,10 +6,7 @@
*/
#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
#include <drm/drm_drv.h>
-#include <drm/drm_mipi_dsi.h>
-#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>
#include <video/mipi_display.h>
@@ -23,448 +20,7 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-mipi-dphy.h>
-
-#define IP_CONF 0x0
-#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
-#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
-#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
-#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
-#define SDI_IFACE_32 BIT(12)
-#define INTERNAL_DATAPATH_32 (0 << 10)
-#define INTERNAL_DATAPATH_16 (1 << 10)
-#define INTERNAL_DATAPATH_8 (3 << 10)
-#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
-#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
-#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
-#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
-
-#define MCTL_MAIN_DATA_CTL 0x4
-#define TE_MIPI_POLLING_EN BIT(25)
-#define TE_HW_POLLING_EN BIT(24)
-#define DISP_EOT_GEN BIT(18)
-#define HOST_EOT_GEN BIT(17)
-#define DISP_GEN_CHECKSUM BIT(16)
-#define DISP_GEN_ECC BIT(15)
-#define BTA_EN BIT(14)
-#define READ_EN BIT(13)
-#define REG_TE_EN BIT(12)
-#define IF_TE_EN(x) BIT(8 + (x))
-#define TVG_SEL BIT(6)
-#define VID_EN BIT(5)
-#define IF_VID_SELECT(x) ((x) << 2)
-#define IF_VID_SELECT_MASK GENMASK(3, 2)
-#define IF_VID_MODE BIT(1)
-#define LINK_EN BIT(0)
-
-#define MCTL_MAIN_PHY_CTL 0x8
-#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
-#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
-#define HS_INVERT_CLK BIT(17)
-#define SWAP_PINS_CLK BIT(16)
-#define HS_SKEWCAL_EN BIT(15)
-#define WAIT_BURST_TIME(x) ((x) << 10)
-#define DATA_ULPM_EN(x) BIT(6 + (x))
-#define CLK_ULPM_EN BIT(5)
-#define CLK_CONTINUOUS BIT(4)
-#define DATA_LANE_EN(x) BIT((x) - 1)
-
-#define MCTL_MAIN_EN 0xc
-#define DATA_FORCE_STOP BIT(17)
-#define CLK_FORCE_STOP BIT(16)
-#define IF_EN(x) BIT(13 + (x))
-#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
-#define CLK_LANE_ULPM_REQ BIT(8)
-#define DATA_LANE_START(x) BIT(4 + (x))
-#define CLK_LANE_EN BIT(3)
-#define PLL_START BIT(0)
-
-#define MCTL_DPHY_CFG0 0x10
-#define DPHY_C_RSTB BIT(20)
-#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
-#define DPHY_PLL_PDN BIT(10)
-#define DPHY_CMN_PDN BIT(9)
-#define DPHY_C_PDN BIT(8)
-#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
-#define DPHY_ALL_D_PDN GENMASK(7, 4)
-#define DPHY_PLL_PSO BIT(1)
-#define DPHY_CMN_PSO BIT(0)
-
-#define MCTL_DPHY_TIMEOUT1 0x14
-#define HSTX_TIMEOUT(x) ((x) << 4)
-#define HSTX_TIMEOUT_MAX GENMASK(17, 0)
-#define CLK_DIV(x) (x)
-#define CLK_DIV_MAX GENMASK(3, 0)
-
-#define MCTL_DPHY_TIMEOUT2 0x18
-#define LPRX_TIMEOUT(x) (x)
-
-#define MCTL_ULPOUT_TIME 0x1c
-#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
-#define CLK_LANE_ULPOUT_TIME(x) (x)
-
-#define MCTL_3DVIDEO_CTL 0x20
-#define VID_VSYNC_3D_EN BIT(7)
-#define VID_VSYNC_3D_LR BIT(5)
-#define VID_VSYNC_3D_SECOND_EN BIT(4)
-#define VID_VSYNC_3DFORMAT_LINE (0 << 2)
-#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
-#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
-#define VID_VSYNC_3DMODE_OFF 0
-#define VID_VSYNC_3DMODE_PORTRAIT 1
-#define VID_VSYNC_3DMODE_LANDSCAPE 2
-
-#define MCTL_MAIN_STS 0x24
-#define MCTL_MAIN_STS_CTL 0x130
-#define MCTL_MAIN_STS_CLR 0x150
-#define MCTL_MAIN_STS_FLAG 0x170
-#define HS_SKEWCAL_DONE BIT(11)
-#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
-#define LPRX_TIMEOUT_ERR BIT(7)
-#define HSTX_TIMEOUT_ERR BIT(6)
-#define DATA_LANE_RDY(l) BIT(2 + (l))
-#define CLK_LANE_RDY BIT(1)
-#define PLL_LOCKED BIT(0)
-
-#define MCTL_DPHY_ERR 0x28
-#define MCTL_DPHY_ERR_CTL1 0x148
-#define MCTL_DPHY_ERR_CLR 0x168
-#define MCTL_DPHY_ERR_FLAG 0x188
-#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
-#define ERR_CONTROL(l) BIT(14 + (l))
-#define ERR_SYNESC(l) BIT(10 + (l))
-#define ERR_ESC(l) BIT(6 + (l))
-
-#define MCTL_DPHY_ERR_CTL2 0x14c
-#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
-#define ERR_CONTROL_EDGE(l) BIT(8 + (l))
-#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
-#define ERR_ESC_EDGE(l) BIT(0 + (l))
-
-#define MCTL_LANE_STS 0x2c
-#define PPI_C_TX_READY_HS BIT(18)
-#define DPHY_PLL_LOCK BIT(17)
-#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
-#define LANE_STATE_START 0
-#define LANE_STATE_IDLE 1
-#define LANE_STATE_WRITE 2
-#define LANE_STATE_ULPM 3
-#define LANE_STATE_READ 4
-#define DATA_LANE_STATE(l, val) \
- (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
-#define CLK_LANE_STATE_HS 2
-#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
-
-#define DSC_MODE_CTL 0x30
-#define DSC_MODE_EN BIT(0)
-
-#define DSC_CMD_SEND 0x34
-#define DSC_SEND_PPS BIT(0)
-#define DSC_EXECUTE_QUEUE BIT(1)
-
-#define DSC_PPS_WRDAT 0x38
-
-#define DSC_MODE_STS 0x3c
-#define DSC_PPS_DONE BIT(1)
-#define DSC_EXEC_DONE BIT(2)
-
-#define CMD_MODE_CTL 0x70
-#define IF_LP_EN(x) BIT(9 + (x))
-#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
-
-#define CMD_MODE_CTL2 0x74
-#define TE_TIMEOUT(x) ((x) << 11)
-#define FILL_VALUE(x) ((x) << 3)
-#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
-#define ARB_ROUND_ROBIN_MODE BIT(0)
-
-#define CMD_MODE_STS 0x78
-#define CMD_MODE_STS_CTL 0x134
-#define CMD_MODE_STS_CLR 0x154
-#define CMD_MODE_STS_FLAG 0x174
-#define ERR_IF_UNDERRUN(x) BIT(4 + (x))
-#define ERR_UNWANTED_READ BIT(3)
-#define ERR_TE_MISS BIT(2)
-#define ERR_NO_TE BIT(1)
-#define CSM_RUNNING BIT(0)
-
-#define DIRECT_CMD_SEND 0x80
-
-#define DIRECT_CMD_MAIN_SETTINGS 0x84
-#define TRIGGER_VAL(x) ((x) << 25)
-#define CMD_LP_EN BIT(24)
-#define CMD_SIZE(x) ((x) << 16)
-#define CMD_VCHAN_ID(x) ((x) << 14)
-#define CMD_DATATYPE(x) ((x) << 8)
-#define CMD_LONG BIT(3)
-#define WRITE_CMD 0
-#define READ_CMD 1
-#define TE_REQ 4
-#define TRIGGER_REQ 5
-#define BTA_REQ 6
-
-#define DIRECT_CMD_STS 0x88
-#define DIRECT_CMD_STS_CTL 0x138
-#define DIRECT_CMD_STS_CLR 0x158
-#define DIRECT_CMD_STS_FLAG 0x178
-#define RCVD_ACK_VAL(val) ((val) >> 16)
-#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
-#define READ_COMPLETED_WITH_ERR BIT(10)
-#define BTA_FINISHED BIT(9)
-#define BTA_COMPLETED BIT(8)
-#define TE_RCVD BIT(7)
-#define TRIGGER_RCVD BIT(6)
-#define ACK_WITH_ERR_RCVD BIT(5)
-#define ACK_RCVD BIT(4)
-#define READ_COMPLETED BIT(3)
-#define TRIGGER_COMPLETED BIT(2)
-#define WRITE_COMPLETED BIT(1)
-#define SENDING_CMD BIT(0)
-
-#define DIRECT_CMD_STOP_READ 0x8c
-
-#define DIRECT_CMD_WRDATA 0x90
-
-#define DIRECT_CMD_FIFO_RST 0x94
-
-#define DIRECT_CMD_RDDATA 0xa0
-
-#define DIRECT_CMD_RD_PROPS 0xa4
-#define RD_DCS BIT(18)
-#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
-#define RD_SIZE(val) ((val) & GENMASK(15, 0))
-
-#define DIRECT_CMD_RD_STS 0xa8
-#define DIRECT_CMD_RD_STS_CTL 0x13c
-#define DIRECT_CMD_RD_STS_CLR 0x15c
-#define DIRECT_CMD_RD_STS_FLAG 0x17c
-#define ERR_EOT_WITH_ERR BIT(8)
-#define ERR_MISSING_EOT BIT(7)
-#define ERR_WRONG_LENGTH BIT(6)
-#define ERR_OVERSIZE BIT(5)
-#define ERR_RECEIVE BIT(4)
-#define ERR_UNDECODABLE BIT(3)
-#define ERR_CHECKSUM BIT(2)
-#define ERR_UNCORRECTABLE BIT(1)
-#define ERR_FIXED BIT(0)
-
-#define VID_MAIN_CTL 0xb0
-#define VID_IGNORE_MISS_VSYNC BIT(31)
-#define VID_FIELD_SW BIT(28)
-#define VID_INTERLACED_EN BIT(27)
-#define RECOVERY_MODE(x) ((x) << 25)
-#define RECOVERY_MODE_NEXT_HSYNC 0
-#define RECOVERY_MODE_NEXT_STOP_POINT 2
-#define RECOVERY_MODE_NEXT_VSYNC 3
-#define REG_BLKEOL_MODE(x) ((x) << 23)
-#define REG_BLKLINE_MODE(x) ((x) << 21)
-#define REG_BLK_MODE_NULL_PKT 0
-#define REG_BLK_MODE_BLANKING_PKT 1
-#define REG_BLK_MODE_LP 2
-#define SYNC_PULSE_HORIZONTAL BIT(20)
-#define SYNC_PULSE_ACTIVE BIT(19)
-#define BURST_MODE BIT(18)
-#define VID_PIXEL_MODE_MASK GENMASK(17, 14)
-#define VID_PIXEL_MODE_RGB565 (0 << 14)
-#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
-#define VID_PIXEL_MODE_RGB666 (2 << 14)
-#define VID_PIXEL_MODE_RGB888 (3 << 14)
-#define VID_PIXEL_MODE_RGB101010 (4 << 14)
-#define VID_PIXEL_MODE_RGB121212 (5 << 14)
-#define VID_PIXEL_MODE_YUV420 (8 << 14)
-#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
-#define VID_PIXEL_MODE_YUV422 (10 << 14)
-#define VID_PIXEL_MODE_YUV422_24B (11 << 14)
-#define VID_PIXEL_MODE_DSC_COMP (12 << 14)
-#define VID_DATATYPE(x) ((x) << 8)
-#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
-#define STOP_MODE(x) ((x) << 2)
-#define START_MODE(x) (x)
-
-#define VID_VSIZE1 0xb4
-#define VFP_LEN(x) ((x) << 12)
-#define VBP_LEN(x) ((x) << 6)
-#define VSA_LEN(x) (x)
-
-#define VID_VSIZE2 0xb8
-#define VACT_LEN(x) (x)
-
-#define VID_HSIZE1 0xc0
-#define HBP_LEN(x) ((x) << 16)
-#define HSA_LEN(x) (x)
-
-#define VID_HSIZE2 0xc4
-#define HFP_LEN(x) ((x) << 16)
-#define HACT_LEN(x) (x)
-
-#define VID_BLKSIZE1 0xcc
-#define BLK_EOL_PKT_LEN(x) ((x) << 15)
-#define BLK_LINE_EVENT_PKT_LEN(x) (x)
-
-#define VID_BLKSIZE2 0xd0
-#define BLK_LINE_PULSE_PKT_LEN(x) (x)
-
-#define VID_PKT_TIME 0xd8
-#define BLK_EOL_DURATION(x) (x)
-
-#define VID_DPHY_TIME 0xdc
-#define REG_WAKEUP_TIME(x) ((x) << 17)
-#define REG_LINE_DURATION(x) (x)
-
-#define VID_ERR_COLOR1 0xe0
-#define COL_GREEN(x) ((x) << 12)
-#define COL_RED(x) (x)
-
-#define VID_ERR_COLOR2 0xe4
-#define PAD_VAL(x) ((x) << 12)
-#define COL_BLUE(x) (x)
-
-#define VID_VPOS 0xe8
-#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
-#define LINE_POS(val) ((val) & GENMASK(1, 0))
-
-#define VID_HPOS 0xec
-#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
-#define HORIZ_POS(val) ((val) & GENMASK(2, 0))
-
-#define VID_MODE_STS 0xf0
-#define VID_MODE_STS_CTL 0x140
-#define VID_MODE_STS_CLR 0x160
-#define VID_MODE_STS_FLAG 0x180
-#define VSG_RECOVERY BIT(10)
-#define ERR_VRS_WRONG_LEN BIT(9)
-#define ERR_LONG_READ BIT(8)
-#define ERR_LINE_WRITE BIT(7)
-#define ERR_BURST_WRITE BIT(6)
-#define ERR_SMALL_HEIGHT BIT(5)
-#define ERR_SMALL_LEN BIT(4)
-#define ERR_MISSING_VSYNC BIT(3)
-#define ERR_MISSING_HSYNC BIT(2)
-#define ERR_MISSING_DATA BIT(1)
-#define VSG_RUNNING BIT(0)
-
-#define VID_VCA_SETTING1 0xf4
-#define BURST_LP BIT(16)
-#define MAX_BURST_LIMIT(x) (x)
-
-#define VID_VCA_SETTING2 0xf8
-#define MAX_LINE_LIMIT(x) ((x) << 16)
-#define EXACT_BURST_LIMIT(x) (x)
-
-#define TVG_CTL 0xfc
-#define TVG_STRIPE_SIZE(x) ((x) << 5)
-#define TVG_MODE_MASK GENMASK(4, 3)
-#define TVG_MODE_SINGLE_COLOR (0 << 3)
-#define TVG_MODE_VSTRIPES (2 << 3)
-#define TVG_MODE_HSTRIPES (3 << 3)
-#define TVG_STOPMODE_MASK GENMASK(2, 1)
-#define TVG_STOPMODE_EOF (0 << 1)
-#define TVG_STOPMODE_EOL (1 << 1)
-#define TVG_STOPMODE_NOW (2 << 1)
-#define TVG_RUN BIT(0)
-
-#define TVG_IMG_SIZE 0x100
-#define TVG_NBLINES(x) ((x) << 16)
-#define TVG_LINE_SIZE(x) (x)
-
-#define TVG_COLOR1 0x104
-#define TVG_COL1_GREEN(x) ((x) << 12)
-#define TVG_COL1_RED(x) (x)
-
-#define TVG_COLOR1_BIS 0x108
-#define TVG_COL1_BLUE(x) (x)
-
-#define TVG_COLOR2 0x10c
-#define TVG_COL2_GREEN(x) ((x) << 12)
-#define TVG_COL2_RED(x) (x)
-
-#define TVG_COLOR2_BIS 0x110
-#define TVG_COL2_BLUE(x) (x)
-
-#define TVG_STS 0x114
-#define TVG_STS_CTL 0x144
-#define TVG_STS_CLR 0x164
-#define TVG_STS_FLAG 0x184
-#define TVG_STS_RUNNING BIT(0)
-
-#define STS_CTL_EDGE(e) ((e) << 16)
-
-#define DPHY_LANES_MAP 0x198
-#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
-
-#define DPI_IRQ_EN 0x1a0
-#define DPI_IRQ_CLR 0x1a4
-#define DPI_IRQ_STS 0x1a8
-#define PIXEL_BUF_OVERFLOW BIT(0)
-
-#define DPI_CFG 0x1ac
-#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
-#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
-
-#define TEST_GENERIC 0x1f0
-#define TEST_STATUS(x) ((x) >> 16)
-#define TEST_CTRL(x) (x)
-
-#define ID_REG 0x1fc
-#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
-#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
-#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
-#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
-#define REV_MINOR(x) ((x) & GENMASK(3, 0))
-
-#define DSI_OUTPUT_PORT 0
-#define DSI_INPUT_PORT(inputid) (1 + (inputid))
-
-#define DSI_HBP_FRAME_OVERHEAD 12
-#define DSI_HSA_FRAME_OVERHEAD 14
-#define DSI_HFP_FRAME_OVERHEAD 6
-#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
-#define DSI_BLANKING_FRAME_OVERHEAD 6
-#define DSI_NULL_FRAME_OVERHEAD 6
-#define DSI_EOT_PKT_SIZE 4
-
-struct cdns_dsi_output {
- struct mipi_dsi_device *dev;
- struct drm_panel *panel;
- struct drm_bridge *bridge;
- union phy_configure_opts phy_opts;
-};
-
-enum cdns_dsi_input_id {
- CDNS_SDI_INPUT,
- CDNS_DPI_INPUT,
- CDNS_DSC_INPUT,
-};
-
-struct cdns_dsi_cfg {
- unsigned int hfp;
- unsigned int hsa;
- unsigned int hbp;
- unsigned int hact;
- unsigned int htotal;
-};
-
-struct cdns_dsi_input {
- enum cdns_dsi_input_id id;
- struct drm_bridge bridge;
-};
-
-struct cdns_dsi {
- struct mipi_dsi_host base;
- void __iomem *regs;
- struct cdns_dsi_input input;
- struct cdns_dsi_output output;
- unsigned int direct_cmd_fifo_depth;
- unsigned int rx_fifo_depth;
- struct completion direct_cmd_comp;
- struct clk *dsi_p_clk;
- struct reset_control *dsi_p_rst;
- struct clk *dsi_sys_clk;
- bool link_initialized;
- bool phy_initialized;
- struct phy *dphy;
-};
+#include "cdns-dsi-core.h"
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
new file mode 100644
index 000000000000..65cc77f19b39
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
@@ -0,0 +1,458 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright: 2017 Cadence Design Systems, Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+
+#ifndef CDNS_DSI_H
+#define CDNS_DSI_H
+
+#include <drm/drm_bridge.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-mipi-dphy.h>
+
+#define IP_CONF 0x0
+#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
+#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
+#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
+#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
+#define SDI_IFACE_32 BIT(12)
+#define INTERNAL_DATAPATH_32 (0 << 10)
+#define INTERNAL_DATAPATH_16 (1 << 10)
+#define INTERNAL_DATAPATH_8 (3 << 10)
+#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
+#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
+#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
+#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
+
+#define MCTL_MAIN_DATA_CTL 0x4
+#define TE_MIPI_POLLING_EN BIT(25)
+#define TE_HW_POLLING_EN BIT(24)
+#define DISP_EOT_GEN BIT(18)
+#define HOST_EOT_GEN BIT(17)
+#define DISP_GEN_CHECKSUM BIT(16)
+#define DISP_GEN_ECC BIT(15)
+#define BTA_EN BIT(14)
+#define READ_EN BIT(13)
+#define REG_TE_EN BIT(12)
+#define IF_TE_EN(x) BIT(8 + (x))
+#define TVG_SEL BIT(6)
+#define VID_EN BIT(5)
+#define IF_VID_SELECT(x) ((x) << 2)
+#define IF_VID_SELECT_MASK GENMASK(3, 2)
+#define IF_VID_MODE BIT(1)
+#define LINK_EN BIT(0)
+
+#define MCTL_MAIN_PHY_CTL 0x8
+#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
+#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
+#define HS_INVERT_CLK BIT(17)
+#define SWAP_PINS_CLK BIT(16)
+#define HS_SKEWCAL_EN BIT(15)
+#define WAIT_BURST_TIME(x) ((x) << 10)
+#define DATA_ULPM_EN(x) BIT(6 + (x))
+#define CLK_ULPM_EN BIT(5)
+#define CLK_CONTINUOUS BIT(4)
+#define DATA_LANE_EN(x) BIT((x) - 1)
+
+#define MCTL_MAIN_EN 0xc
+#define DATA_FORCE_STOP BIT(17)
+#define CLK_FORCE_STOP BIT(16)
+#define IF_EN(x) BIT(13 + (x))
+#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
+#define CLK_LANE_ULPM_REQ BIT(8)
+#define DATA_LANE_START(x) BIT(4 + (x))
+#define CLK_LANE_EN BIT(3)
+#define PLL_START BIT(0)
+
+#define MCTL_DPHY_CFG0 0x10
+#define DPHY_C_RSTB BIT(20)
+#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
+#define DPHY_PLL_PDN BIT(10)
+#define DPHY_CMN_PDN BIT(9)
+#define DPHY_C_PDN BIT(8)
+#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
+#define DPHY_ALL_D_PDN GENMASK(7, 4)
+#define DPHY_PLL_PSO BIT(1)
+#define DPHY_CMN_PSO BIT(0)
+
+#define MCTL_DPHY_TIMEOUT1 0x14
+#define HSTX_TIMEOUT(x) ((x) << 4)
+#define HSTX_TIMEOUT_MAX GENMASK(17, 0)
+#define CLK_DIV(x) (x)
+#define CLK_DIV_MAX GENMASK(3, 0)
+
+#define MCTL_DPHY_TIMEOUT2 0x18
+#define LPRX_TIMEOUT(x) (x)
+
+#define MCTL_ULPOUT_TIME 0x1c
+#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
+#define CLK_LANE_ULPOUT_TIME(x) (x)
+
+#define MCTL_3DVIDEO_CTL 0x20
+#define VID_VSYNC_3D_EN BIT(7)
+#define VID_VSYNC_3D_LR BIT(5)
+#define VID_VSYNC_3D_SECOND_EN BIT(4)
+#define VID_VSYNC_3DFORMAT_LINE (0 << 2)
+#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
+#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
+#define VID_VSYNC_3DMODE_OFF 0
+#define VID_VSYNC_3DMODE_PORTRAIT 1
+#define VID_VSYNC_3DMODE_LANDSCAPE 2
+
+#define MCTL_MAIN_STS 0x24
+#define MCTL_MAIN_STS_CTL 0x130
+#define MCTL_MAIN_STS_CLR 0x150
+#define MCTL_MAIN_STS_FLAG 0x170
+#define HS_SKEWCAL_DONE BIT(11)
+#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
+#define LPRX_TIMEOUT_ERR BIT(7)
+#define HSTX_TIMEOUT_ERR BIT(6)
+#define DATA_LANE_RDY(l) BIT(2 + (l))
+#define CLK_LANE_RDY BIT(1)
+#define PLL_LOCKED BIT(0)
+
+#define MCTL_DPHY_ERR 0x28
+#define MCTL_DPHY_ERR_CTL1 0x148
+#define MCTL_DPHY_ERR_CLR 0x168
+#define MCTL_DPHY_ERR_FLAG 0x188
+#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
+#define ERR_CONTROL(l) BIT(14 + (l))
+#define ERR_SYNESC(l) BIT(10 + (l))
+#define ERR_ESC(l) BIT(6 + (l))
+
+#define MCTL_DPHY_ERR_CTL2 0x14c
+#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
+#define ERR_CONTROL_EDGE(l) BIT(8 + (l))
+#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
+#define ERR_ESC_EDGE(l) BIT(0 + (l))
+
+#define MCTL_LANE_STS 0x2c
+#define PPI_C_TX_READY_HS BIT(18)
+#define DPHY_PLL_LOCK BIT(17)
+#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
+#define LANE_STATE_START 0
+#define LANE_STATE_IDLE 1
+#define LANE_STATE_WRITE 2
+#define LANE_STATE_ULPM 3
+#define LANE_STATE_READ 4
+#define DATA_LANE_STATE(l, val) \
+ (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
+#define CLK_LANE_STATE_HS 2
+#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
+
+#define DSC_MODE_CTL 0x30
+#define DSC_MODE_EN BIT(0)
+
+#define DSC_CMD_SEND 0x34
+#define DSC_SEND_PPS BIT(0)
+#define DSC_EXECUTE_QUEUE BIT(1)
+
+#define DSC_PPS_WRDAT 0x38
+
+#define DSC_MODE_STS 0x3c
+#define DSC_PPS_DONE BIT(1)
+#define DSC_EXEC_DONE BIT(2)
+
+#define CMD_MODE_CTL 0x70
+#define IF_LP_EN(x) BIT(9 + (x))
+#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
+
+#define CMD_MODE_CTL2 0x74
+#define TE_TIMEOUT(x) ((x) << 11)
+#define FILL_VALUE(x) ((x) << 3)
+#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
+#define ARB_ROUND_ROBIN_MODE BIT(0)
+
+#define CMD_MODE_STS 0x78
+#define CMD_MODE_STS_CTL 0x134
+#define CMD_MODE_STS_CLR 0x154
+#define CMD_MODE_STS_FLAG 0x174
+#define ERR_IF_UNDERRUN(x) BIT(4 + (x))
+#define ERR_UNWANTED_READ BIT(3)
+#define ERR_TE_MISS BIT(2)
+#define ERR_NO_TE BIT(1)
+#define CSM_RUNNING BIT(0)
+
+#define DIRECT_CMD_SEND 0x80
+
+#define DIRECT_CMD_MAIN_SETTINGS 0x84
+#define TRIGGER_VAL(x) ((x) << 25)
+#define CMD_LP_EN BIT(24)
+#define CMD_SIZE(x) ((x) << 16)
+#define CMD_VCHAN_ID(x) ((x) << 14)
+#define CMD_DATATYPE(x) ((x) << 8)
+#define CMD_LONG BIT(3)
+#define WRITE_CMD 0
+#define READ_CMD 1
+#define TE_REQ 4
+#define TRIGGER_REQ 5
+#define BTA_REQ 6
+
+#define DIRECT_CMD_STS 0x88
+#define DIRECT_CMD_STS_CTL 0x138
+#define DIRECT_CMD_STS_CLR 0x158
+#define DIRECT_CMD_STS_FLAG 0x178
+#define RCVD_ACK_VAL(val) ((val) >> 16)
+#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
+#define READ_COMPLETED_WITH_ERR BIT(10)
+#define BTA_FINISHED BIT(9)
+#define BTA_COMPLETED BIT(8)
+#define TE_RCVD BIT(7)
+#define TRIGGER_RCVD BIT(6)
+#define ACK_WITH_ERR_RCVD BIT(5)
+#define ACK_RCVD BIT(4)
+#define READ_COMPLETED BIT(3)
+#define TRIGGER_COMPLETED BIT(2)
+#define WRITE_COMPLETED BIT(1)
+#define SENDING_CMD BIT(0)
+
+#define DIRECT_CMD_STOP_READ 0x8c
+
+#define DIRECT_CMD_WRDATA 0x90
+
+#define DIRECT_CMD_FIFO_RST 0x94
+
+#define DIRECT_CMD_RDDATA 0xa0
+
+#define DIRECT_CMD_RD_PROPS 0xa4
+#define RD_DCS BIT(18)
+#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
+#define RD_SIZE(val) ((val) & GENMASK(15, 0))
+
+#define DIRECT_CMD_RD_STS 0xa8
+#define DIRECT_CMD_RD_STS_CTL 0x13c
+#define DIRECT_CMD_RD_STS_CLR 0x15c
+#define DIRECT_CMD_RD_STS_FLAG 0x17c
+#define ERR_EOT_WITH_ERR BIT(8)
+#define ERR_MISSING_EOT BIT(7)
+#define ERR_WRONG_LENGTH BIT(6)
+#define ERR_OVERSIZE BIT(5)
+#define ERR_RECEIVE BIT(4)
+#define ERR_UNDECODABLE BIT(3)
+#define ERR_CHECKSUM BIT(2)
+#define ERR_UNCORRECTABLE BIT(1)
+#define ERR_FIXED BIT(0)
+
+#define VID_MAIN_CTL 0xb0
+#define VID_IGNORE_MISS_VSYNC BIT(31)
+#define VID_FIELD_SW BIT(28)
+#define VID_INTERLACED_EN BIT(27)
+#define RECOVERY_MODE(x) ((x) << 25)
+#define RECOVERY_MODE_NEXT_HSYNC 0
+#define RECOVERY_MODE_NEXT_STOP_POINT 2
+#define RECOVERY_MODE_NEXT_VSYNC 3
+#define REG_BLKEOL_MODE(x) ((x) << 23)
+#define REG_BLKLINE_MODE(x) ((x) << 21)
+#define REG_BLK_MODE_NULL_PKT 0
+#define REG_BLK_MODE_BLANKING_PKT 1
+#define REG_BLK_MODE_LP 2
+#define SYNC_PULSE_HORIZONTAL BIT(20)
+#define SYNC_PULSE_ACTIVE BIT(19)
+#define BURST_MODE BIT(18)
+#define VID_PIXEL_MODE_MASK GENMASK(17, 14)
+#define VID_PIXEL_MODE_RGB565 (0 << 14)
+#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
+#define VID_PIXEL_MODE_RGB666 (2 << 14)
+#define VID_PIXEL_MODE_RGB888 (3 << 14)
+#define VID_PIXEL_MODE_RGB101010 (4 << 14)
+#define VID_PIXEL_MODE_RGB121212 (5 << 14)
+#define VID_PIXEL_MODE_YUV420 (8 << 14)
+#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
+#define VID_PIXEL_MODE_YUV422 (10 << 14)
+#define VID_PIXEL_MODE_YUV422_24B (11 << 14)
+#define VID_PIXEL_MODE_DSC_COMP (12 << 14)
+#define VID_DATATYPE(x) ((x) << 8)
+#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
+#define STOP_MODE(x) ((x) << 2)
+#define START_MODE(x) (x)
+
+#define VID_VSIZE1 0xb4
+#define VFP_LEN(x) ((x) << 12)
+#define VBP_LEN(x) ((x) << 6)
+#define VSA_LEN(x) (x)
+
+#define VID_VSIZE2 0xb8
+#define VACT_LEN(x) (x)
+
+#define VID_HSIZE1 0xc0
+#define HBP_LEN(x) ((x) << 16)
+#define HSA_LEN(x) (x)
+
+#define VID_HSIZE2 0xc4
+#define HFP_LEN(x) ((x) << 16)
+#define HACT_LEN(x) (x)
+
+#define VID_BLKSIZE1 0xcc
+#define BLK_EOL_PKT_LEN(x) ((x) << 15)
+#define BLK_LINE_EVENT_PKT_LEN(x) (x)
+
+#define VID_BLKSIZE2 0xd0
+#define BLK_LINE_PULSE_PKT_LEN(x) (x)
+
+#define VID_PKT_TIME 0xd8
+#define BLK_EOL_DURATION(x) (x)
+
+#define VID_DPHY_TIME 0xdc
+#define REG_WAKEUP_TIME(x) ((x) << 17)
+#define REG_LINE_DURATION(x) (x)
+
+#define VID_ERR_COLOR1 0xe0
+#define COL_GREEN(x) ((x) << 12)
+#define COL_RED(x) (x)
+
+#define VID_ERR_COLOR2 0xe4
+#define PAD_VAL(x) ((x) << 12)
+#define COL_BLUE(x) (x)
+
+#define VID_VPOS 0xe8
+#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
+#define LINE_POS(val) ((val) & GENMASK(1, 0))
+
+#define VID_HPOS 0xec
+#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
+#define HORIZ_POS(val) ((val) & GENMASK(2, 0))
+
+#define VID_MODE_STS 0xf0
+#define VID_MODE_STS_CTL 0x140
+#define VID_MODE_STS_CLR 0x160
+#define VID_MODE_STS_FLAG 0x180
+#define VSG_RECOVERY BIT(10)
+#define ERR_VRS_WRONG_LEN BIT(9)
+#define ERR_LONG_READ BIT(8)
+#define ERR_LINE_WRITE BIT(7)
+#define ERR_BURST_WRITE BIT(6)
+#define ERR_SMALL_HEIGHT BIT(5)
+#define ERR_SMALL_LEN BIT(4)
+#define ERR_MISSING_VSYNC BIT(3)
+#define ERR_MISSING_HSYNC BIT(2)
+#define ERR_MISSING_DATA BIT(1)
+#define VSG_RUNNING BIT(0)
+
+#define VID_VCA_SETTING1 0xf4
+#define BURST_LP BIT(16)
+#define MAX_BURST_LIMIT(x) (x)
+
+#define VID_VCA_SETTING2 0xf8
+#define MAX_LINE_LIMIT(x) ((x) << 16)
+#define EXACT_BURST_LIMIT(x) (x)
+
+#define TVG_CTL 0xfc
+#define TVG_STRIPE_SIZE(x) ((x) << 5)
+#define TVG_MODE_MASK GENMASK(4, 3)
+#define TVG_MODE_SINGLE_COLOR (0 << 3)
+#define TVG_MODE_VSTRIPES (2 << 3)
+#define TVG_MODE_HSTRIPES (3 << 3)
+#define TVG_STOPMODE_MASK GENMASK(2, 1)
+#define TVG_STOPMODE_EOF (0 << 1)
+#define TVG_STOPMODE_EOL (1 << 1)
+#define TVG_STOPMODE_NOW (2 << 1)
+#define TVG_RUN BIT(0)
+
+#define TVG_IMG_SIZE 0x100
+#define TVG_NBLINES(x) ((x) << 16)
+#define TVG_LINE_SIZE(x) (x)
+
+#define TVG_COLOR1 0x104
+#define TVG_COL1_GREEN(x) ((x) << 12)
+#define TVG_COL1_RED(x) (x)
+
+#define TVG_COLOR1_BIS 0x108
+#define TVG_COL1_BLUE(x) (x)
+
+#define TVG_COLOR2 0x10c
+#define TVG_COL2_GREEN(x) ((x) << 12)
+#define TVG_COL2_RED(x) (x)
+
+#define TVG_COLOR2_BIS 0x110
+#define TVG_COL2_BLUE(x) (x)
+
+#define TVG_STS 0x114
+#define TVG_STS_CTL 0x144
+#define TVG_STS_CLR 0x164
+#define TVG_STS_FLAG 0x184
+#define TVG_STS_RUNNING BIT(0)
+
+#define STS_CTL_EDGE(e) ((e) << 16)
+
+#define DPHY_LANES_MAP 0x198
+#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
+
+#define DPI_IRQ_EN 0x1a0
+#define DPI_IRQ_CLR 0x1a4
+#define DPI_IRQ_STS 0x1a8
+#define PIXEL_BUF_OVERFLOW BIT(0)
+
+#define DPI_CFG 0x1ac
+#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
+#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
+
+#define TEST_GENERIC 0x1f0
+#define TEST_STATUS(x) ((x) >> 16)
+#define TEST_CTRL(x) (x)
+
+#define ID_REG 0x1fc
+#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
+#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
+#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
+#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
+#define REV_MINOR(x) ((x) & GENMASK(3, 0))
+
+#define DSI_OUTPUT_PORT 0
+#define DSI_INPUT_PORT(inputid) (1 + (inputid))
+
+#define DSI_HBP_FRAME_OVERHEAD 12
+#define DSI_HSA_FRAME_OVERHEAD 14
+#define DSI_HFP_FRAME_OVERHEAD 6
+#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
+#define DSI_BLANKING_FRAME_OVERHEAD 6
+#define DSI_NULL_FRAME_OVERHEAD 6
+#define DSI_EOT_PKT_SIZE 4
+
+struct cdns_dsi_output {
+ struct mipi_dsi_device *dev;
+ struct drm_panel *panel;
+ struct drm_bridge *bridge;
+ union phy_configure_opts phy_opts;
+};
+
+enum cdns_dsi_input_id {
+ CDNS_SDI_INPUT,
+ CDNS_DPI_INPUT,
+ CDNS_DSC_INPUT,
+};
+
+struct cdns_dsi_cfg {
+ unsigned int hfp;
+ unsigned int hsa;
+ unsigned int hbp;
+ unsigned int hact;
+ unsigned int htotal;
+};
+
+struct cdns_dsi_input {
+ enum cdns_dsi_input_id id;
+ struct drm_bridge bridge;
+};
+
+struct cdns_dsi {
+ struct mipi_dsi_host base;
+ void __iomem *regs;
+ struct cdns_dsi_input input;
+ struct cdns_dsi_output output;
+ unsigned int direct_cmd_fifo_depth;
+ unsigned int rx_fifo_depth;
+ struct completion direct_cmd_comp;
+ struct clk *dsi_p_clk;
+ struct reset_control *dsi_p_rst;
+ struct clk *dsi_sys_clk;
+ bool link_initialized;
+ bool phy_initialized;
+ struct phy *dphy;
+};
+
+#endif /* !CDNS_DSI_H */
--
2.38.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
` (3 preceding siblings ...)
2022-10-21 17:18 ` [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file Rahul T R
@ 2022-10-21 17:18 ` Rahul T R
2022-10-26 6:12 ` Tomi Valkeinen
4 siblings, 1 reply; 10+ messages in thread
From: Rahul T R @ 2022-10-21 17:18 UTC (permalink / raw)
To: dri-devel, robh+dt, krzysztof.kozlowski+dt, tomi.valkeinen
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones,
Rahul T R
Add support for wrapper settings for DSI bridge on
j721e. Also set the DPI input to DPI0
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
drivers/gpu/drm/bridge/cadence/Kconfig | 10 ++++
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c | 37 +++++++++++++-
.../gpu/drm/bridge/cadence/cdns-dsi-core.h | 13 +++++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++++++++++++++++++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++++++
6 files changed, 129 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
index 8fbb46c66094..663a02d96420 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -36,3 +36,13 @@ config DRM_CDNS_DSI
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DPI/DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DSI wrapper. This wrapper adds
+ support to select which DPI input to use for the bridge.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile
index e3d8e9a40784..4cffc8ff71c4 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index cba91247ab26..4b7de38ef1b0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,12 +15,16 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
@@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed: %d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
if (ret)
- goto err_disable_runtime_pm;
+ goto err_deinit_platform;
clk_disable_unprepare(dsi->dsi_p_clk);
return 0;
+err_deinit_platform:
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platform_ops->exit(dsi);
+
err_disable_runtime_pm:
pm_runtime_disable(&pdev->dev);
@@ -857,6 +883,10 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
struct cdns_dsi *dsi = platform_get_drvdata(pdev);
mipi_dsi_host_unregister(&dsi->base);
+
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platform_ops->exit(dsi);
+
pm_runtime_disable(&pdev->dev);
return 0;
@@ -864,6 +894,11 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
static const struct of_device_id cdns_dsi_of_match[] = {
{ .compatible = "cdns,dsi" },
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+ { .compatible = "ti,j721e-dsi",
+ .data = &dsi_ti_j721e_ops,
+ },
+#endif
{ },
};
MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
index 65cc77f19b39..37568b547fbe 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
@@ -439,9 +439,22 @@ struct cdns_dsi_input {
struct drm_bridge bridge;
};
+struct cdns_dsi;
+
+struct dsi_platform_ops {
+ int (*init)(struct cdns_dsi *dsi);
+ void (*exit)(struct cdns_dsi *dsi);
+ void (*enable)(struct cdns_dsi *dsi);
+ void (*disable)(struct cdns_dsi *dsi);
+};
+
struct cdns_dsi {
struct mipi_dsi_host base;
void __iomem *regs;
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+ void __iomem *j721e_regs;
+#endif
+ const struct dsi_platform_ops *platform_ops;
struct cdns_dsi_input input;
struct cdns_dsi_output output;
unsigned int direct_cmd_fifo_depth;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
new file mode 100644
index 000000000000..b5216acb333e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence DSI wrapper
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rahul T R <r-ravikumar@ti.com>
+ */
+
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "cdns-dsi-j721e.h"
+
+#define DSI_WRAP_REVISION 0x0
+#define DSI_WRAP_DPI_CONTROL 0x4
+#define DSI_WRAP_DSC_CONTROL 0x8
+#define DSI_WRAP_DPI_SECURE 0xc
+#define DSI_WRAP_DSI_0_ASF_STATUS 0x10
+
+#define DSI_WRAP_DPI_0_EN BIT(0)
+#define DSI_WRAP_DSI2_MUX_SEL BIT(4)
+
+static int cdns_dsi_j721e_init(struct cdns_dsi *dsi)
+{
+ struct platform_device *pdev = to_platform_device(dsi->base.dev);
+
+ dsi->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
+ return PTR_ERR_OR_ZERO(dsi->j721e_regs);
+}
+
+static void cdns_dsi_j721e_enable(struct cdns_dsi *dsi)
+{
+ /*
+ * Enable DPI0 as its input. DSS0 DPI2 is connected
+ * to DSI DPI0. This is the only supported configuration on
+ * J721E.
+ */
+ writel(DSI_WRAP_DPI_0_EN, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
+}
+
+static void cdns_dsi_j721e_disable(struct cdns_dsi *dsi)
+{
+ /* Put everything to defaults */
+ writel(0, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
+}
+
+const struct dsi_platform_ops dsi_ti_j721e_ops = {
+ .init = cdns_dsi_j721e_init,
+ .enable = cdns_dsi_j721e_enable,
+ .disable = cdns_dsi_j721e_disable,
+};
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
new file mode 100644
index 000000000000..01f3dbd92db2
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI j721e Cadence DSI wrapper
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rahul T R <r-ravikumar@ti.com>
+ */
+
+#ifndef CDNS_DSI_J721E_H
+#define CDNS_DSI_J721E_H
+
+#include "cdns-dsi-core.h"
+
+struct dsi_platform_ops;
+
+extern const struct dsi_platform_ops dsi_ti_j721e_ops;
+
+#endif /* !CDNS_DSI_J721E_H */
--
2.38.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
2022-10-21 17:18 ` [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper Rahul T R
@ 2022-10-26 6:12 ` Tomi Valkeinen
2022-10-31 12:24 ` Rahul T R
0 siblings, 1 reply; 10+ messages in thread
From: Tomi Valkeinen @ 2022-10-26 6:12 UTC (permalink / raw)
To: Rahul T R, dri-devel, robh+dt, krzysztof.kozlowski+dt
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones
Hi,
On 21/10/2022 20:18, Rahul T R wrote:
> Add support for wrapper settings for DSI bridge on
> j721e. Also set the DPI input to DPI0
I think a few more words on the HW layout would be nice. What does the
wrapper do and how is it connected to the DSS.
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> ---
> drivers/gpu/drm/bridge/cadence/Kconfig | 10 ++++
> drivers/gpu/drm/bridge/cadence/Makefile | 1 +
> .../gpu/drm/bridge/cadence/cdns-dsi-core.c | 37 +++++++++++++-
> .../gpu/drm/bridge/cadence/cdns-dsi-core.h | 13 +++++
> .../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++++++++++++++++++
> .../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++++++
> 6 files changed, 129 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
>
> diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
> index 8fbb46c66094..663a02d96420 100644
> --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> @@ -36,3 +36,13 @@ config DRM_CDNS_DSI
> help
> Support Cadence DPI to DSI bridge. This is an internal
> bridge and is meant to be directly embedded in a SoC.
> +
> +if DRM_CDNS_DSI
> +
> +config DRM_CDNS_DSI_J721E
> + bool "J721E Cadence DPI/DSI wrapper support"
> + default y
> + help
> + Support J721E Cadence DPI/DSI wrapper. This wrapper adds
> + support to select which DPI input to use for the bridge.
I'm not sure if the above is quite necessary here. If I understand
right, there's only one way on J721E to mux the DPI signal going to the
DSI. If you write "adds support to select DPI input" it sounds like
there's something to select, and this config somehow enables that
selection for the user.
Perhaps instead just say something like "Support J721E Cadence DPI/DSI
wrapper. The wrapper manages the routing of the DSS DPI signal to the
Cadence DSI.", or something along those lines.
Also, you say "DPI/DSI wrapper". How does this wrap DPI? Isn't this just
a DSI wrapper?
> +endif
> diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile
> index e3d8e9a40784..4cffc8ff71c4 100644
> --- a/drivers/gpu/drm/bridge/cadence/Makefile
> +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> @@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
> obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> cdns-dsi-y := cdns-dsi-core.o
> +cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> index cba91247ab26..4b7de38ef1b0 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> @@ -15,12 +15,16 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/of_graph.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/reset.h>
>
> #include "cdns-dsi-core.h"
> +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> +#include "cdns-dsi-j721e.h"
> +#endif
>
> static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
> {
> @@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
>
> val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
> writel(val, dsi->regs + MCTL_MAIN_EN);
> +
> + if (dsi->platform_ops && dsi->platform_ops->disable)
> + dsi->platform_ops->disable(dsi);
> +
> pm_runtime_put(dsi->base.dev);
> }
>
> @@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
> if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
> return;
>
> + if (dsi->platform_ops && dsi->platform_ops->enable)
> + dsi->platform_ops->enable(dsi);
> +
> mode = &bridge->encoder->crtc->state->adjusted_mode;
> nlanes = output->dev->lanes;
>
> @@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
> goto err_disable_pclk;
> }
>
> + dsi->platform_ops = of_device_get_match_data(&pdev->dev);
> +
> val = readl(dsi->regs + IP_CONF);
> dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
> dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
> @@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
> dsi->base.dev = &pdev->dev;
> dsi->base.ops = &cdns_dsi_ops;
>
> + if (dsi->platform_ops && dsi->platform_ops->init) {
> + ret = dsi->platform_ops->init(dsi);
> + if (ret != 0) {
> + dev_err(&pdev->dev, "platform initialization failed: %d\n",
> + ret);
> + goto err_disable_runtime_pm;
> + }
> + }
> +
> ret = mipi_dsi_host_register(&dsi->base);
> if (ret)
> - goto err_disable_runtime_pm;
> + goto err_deinit_platform;
>
> clk_disable_unprepare(dsi->dsi_p_clk);
>
> return 0;
>
> +err_deinit_platform:
> + if (dsi->platform_ops && dsi->platform_ops->exit)
> + dsi->platform_ops->exit(dsi);
> +
> err_disable_runtime_pm:
> pm_runtime_disable(&pdev->dev);
>
> @@ -857,6 +883,10 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
> struct cdns_dsi *dsi = platform_get_drvdata(pdev);
>
> mipi_dsi_host_unregister(&dsi->base);
> +
> + if (dsi->platform_ops && dsi->platform_ops->exit)
> + dsi->platform_ops->exit(dsi);
> +
> pm_runtime_disable(&pdev->dev);
>
> return 0;
> @@ -864,6 +894,11 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
>
> static const struct of_device_id cdns_dsi_of_match[] = {
> { .compatible = "cdns,dsi" },
> +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> + { .compatible = "ti,j721e-dsi",
> + .data = &dsi_ti_j721e_ops,
> + },
I find the above formatting a bit odd. I think this should do fine:
{ .compatible = "ti,j721e-dsi", .data = &dsi_ti_j721e_ops, },
If you want multi-line, then I think the opening { should be on its own
line, similarly to the closing }.
> +#endif
> { },
> };
> MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> index 65cc77f19b39..37568b547fbe 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> @@ -439,9 +439,22 @@ struct cdns_dsi_input {
> struct drm_bridge bridge;
> };
>
> +struct cdns_dsi;
> +
> +struct dsi_platform_ops {
> + int (*init)(struct cdns_dsi *dsi);
> + void (*exit)(struct cdns_dsi *dsi);
I don't think init and exit are the opposites, but rather init and
deinit/uninit.
> + void (*enable)(struct cdns_dsi *dsi);
> + void (*disable)(struct cdns_dsi *dsi);
> +};
> +
> struct cdns_dsi {
> struct mipi_dsi_host base;
> void __iomem *regs;
> +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> + void __iomem *j721e_regs;
> +#endif
> + const struct dsi_platform_ops *platform_ops;
> struct cdns_dsi_input input;
> struct cdns_dsi_output output;
> unsigned int direct_cmd_fifo_depth;
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> new file mode 100644
> index 000000000000..b5216acb333e
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * TI j721e Cadence DSI wrapper
> + *
> + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
> + * Author: Rahul T R <r-ravikumar@ti.com>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include "cdns-dsi-j721e.h"
> +
> +#define DSI_WRAP_REVISION 0x0
> +#define DSI_WRAP_DPI_CONTROL 0x4
> +#define DSI_WRAP_DSC_CONTROL 0x8
> +#define DSI_WRAP_DPI_SECURE 0xc
> +#define DSI_WRAP_DSI_0_ASF_STATUS 0x10
> +
> +#define DSI_WRAP_DPI_0_EN BIT(0)
> +#define DSI_WRAP_DSI2_MUX_SEL BIT(4)
> +
> +static int cdns_dsi_j721e_init(struct cdns_dsi *dsi)
> +{
> + struct platform_device *pdev = to_platform_device(dsi->base.dev);
> +
> + dsi->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
> + return PTR_ERR_OR_ZERO(dsi->j721e_regs);
> +}
> +
> +static void cdns_dsi_j721e_enable(struct cdns_dsi *dsi)
> +{
> + /*
> + * Enable DPI0 as its input. DSS0 DPI2 is connected
> + * to DSI DPI0. This is the only supported configuration on
> + * J721E.
> + */
> + writel(DSI_WRAP_DPI_0_EN, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
> +}
> +
> +static void cdns_dsi_j721e_disable(struct cdns_dsi *dsi)
> +{
> + /* Put everything to defaults */
> + writel(0, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
> +}
> +
> +const struct dsi_platform_ops dsi_ti_j721e_ops = {
> + .init = cdns_dsi_j721e_init,
> + .enable = cdns_dsi_j721e_enable,
> + .disable = cdns_dsi_j721e_disable,
> +};
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> new file mode 100644
> index 000000000000..01f3dbd92db2
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * TI j721e Cadence DSI wrapper
> + *
> + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
> + * Author: Rahul T R <r-ravikumar@ti.com>
> + */
> +
> +#ifndef CDNS_DSI_J721E_H
> +#define CDNS_DSI_J721E_H
> +
> +#include "cdns-dsi-core.h"
> +
> +struct dsi_platform_ops;
You don't need the above line as you already include the cdns-dsi-core.h
> +extern const struct dsi_platform_ops dsi_ti_j721e_ops;
> +
> +#endif /* !CDNS_DSI_J721E_H */
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
2022-10-21 17:18 ` [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence Rahul T R
@ 2022-10-26 6:15 ` Tomi Valkeinen
0 siblings, 0 replies; 10+ messages in thread
From: Tomi Valkeinen @ 2022-10-26 6:15 UTC (permalink / raw)
To: Rahul T R, dri-devel, robh+dt, krzysztof.kozlowski+dt
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones
On 21/10/2022 20:18, Rahul T R wrote:
> Move the cadence dsi bridge under drm/bridge/cadence
> directory, to prepare for adding j721e wrapper
> support
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> ---
> drivers/gpu/drm/bridge/Kconfig | 11 -----------
> drivers/gpu/drm/bridge/Makefile | 1 -
> drivers/gpu/drm/bridge/cadence/Kconfig | 11 +++++++++++
> drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
> .../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} | 0
> 5 files changed, 13 insertions(+), 12 deletions(-)
> rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Tomi
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file
2022-10-21 17:18 ` [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file Rahul T R
@ 2022-10-26 6:16 ` Tomi Valkeinen
0 siblings, 0 replies; 10+ messages in thread
From: Tomi Valkeinen @ 2022-10-26 6:16 UTC (permalink / raw)
To: Rahul T R, dri-devel, robh+dt, krzysztof.kozlowski+dt
Cc: andrzej.hajda, narmstrong, robert.foss, jonas, jernej.skrabec,
airlied, daniel, p.zabel, laurent.pinchart, linux-kernel, jpawar,
sjakhade, mparab, a-bhatia1, devicetree, vigneshr, lee.jones
On 21/10/2022 20:18, Rahul T R wrote:
> Create a header file for cdns dsi and move
> register offsets and structure to header,
> to prepare for adding j721e wrapper support
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> ---
> .../gpu/drm/bridge/cadence/cdns-dsi-core.c | 446 +----------------
> .../gpu/drm/bridge/cadence/cdns-dsi-core.h | 458 ++++++++++++++++++
> 2 files changed, 459 insertions(+), 445 deletions(-)
> create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Tomi
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
2022-10-26 6:12 ` Tomi Valkeinen
@ 2022-10-31 12:24 ` Rahul T R
0 siblings, 0 replies; 10+ messages in thread
From: Rahul T R @ 2022-10-31 12:24 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: dri-devel, robh+dt, krzysztof.kozlowski+dt, andrzej.hajda,
narmstrong, robert.foss, jonas, jernej.skrabec, airlied, daniel,
p.zabel, laurent.pinchart, linux-kernel, jpawar, sjakhade,
mparab, a-bhatia1, devicetree, vigneshr, lee.jones
Hi Tomi,
On 09:12-20221026, Tomi Valkeinen wrote:
> Hi,
>
> On 21/10/2022 20:18, Rahul T R wrote:
> > Add support for wrapper settings for DSI bridge on
> > j721e. Also set the DPI input to DPI0
>
> I think a few more words on the HW layout would be nice. What does the
> wrapper do and how is it connected to the DSS.
>
> > Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> > ---
> > drivers/gpu/drm/bridge/cadence/Kconfig | 10 ++++
> > drivers/gpu/drm/bridge/cadence/Makefile | 1 +
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.c | 37 +++++++++++++-
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.h | 13 +++++
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++++++++++++++++++
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++++++
> > 6 files changed, 129 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
> > index 8fbb46c66094..663a02d96420 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -36,3 +36,13 @@ config DRM_CDNS_DSI
> > help
> > Support Cadence DPI to DSI bridge. This is an internal
> > bridge and is meant to be directly embedded in a SoC.
> > +
> > +if DRM_CDNS_DSI
> > +
> > +config DRM_CDNS_DSI_J721E
> > + bool "J721E Cadence DPI/DSI wrapper support"
> > + default y
> > + help
> > + Support J721E Cadence DPI/DSI wrapper. This wrapper adds
> > + support to select which DPI input to use for the bridge.
>
> I'm not sure if the above is quite necessary here. If I understand right,
> there's only one way on J721E to mux the DPI signal going to the DSI. If you
> write "adds support to select DPI input" it sounds like there's something to
> select, and this config somehow enables that selection for the user.
>
> Perhaps instead just say something like "Support J721E Cadence DPI/DSI
> wrapper. The wrapper manages the routing of the DSS DPI signal to the
> Cadence DSI.", or something along those lines.
>
> Also, you say "DPI/DSI wrapper". How does this wrap DPI? Isn't this just a
> DSI wrapper?
>
> > +endif
> > diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile
> > index e3d8e9a40784..4cffc8ff71c4 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> > cdns-dsi-y := cdns-dsi-core.o
> > +cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > index cba91247ab26..4b7de38ef1b0 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > @@ -15,12 +15,16 @@
> > #include <linux/iopoll.h>
> > #include <linux/module.h>
> > #include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > #include <linux/of_graph.h>
> > #include <linux/platform_device.h>
> > #include <linux/pm_runtime.h>
> > #include <linux/reset.h>
> > #include "cdns-dsi-core.h"
> > +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> > +#include "cdns-dsi-j721e.h"
> > +#endif
> > static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
> > {
> > @@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
> > val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
> > writel(val, dsi->regs + MCTL_MAIN_EN);
> > +
> > + if (dsi->platform_ops && dsi->platform_ops->disable)
> > + dsi->platform_ops->disable(dsi);
> > +
> > pm_runtime_put(dsi->base.dev);
> > }
> > @@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
> > if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
> > return;
> > + if (dsi->platform_ops && dsi->platform_ops->enable)
> > + dsi->platform_ops->enable(dsi);
> > +
> > mode = &bridge->encoder->crtc->state->adjusted_mode;
> > nlanes = output->dev->lanes;
> > @@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
> > goto err_disable_pclk;
> > }
> > + dsi->platform_ops = of_device_get_match_data(&pdev->dev);
> > +
> > val = readl(dsi->regs + IP_CONF);
> > dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
> > dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
> > @@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
> > dsi->base.dev = &pdev->dev;
> > dsi->base.ops = &cdns_dsi_ops;
> > + if (dsi->platform_ops && dsi->platform_ops->init) {
> > + ret = dsi->platform_ops->init(dsi);
> > + if (ret != 0) {
> > + dev_err(&pdev->dev, "platform initialization failed: %d\n",
> > + ret);
> > + goto err_disable_runtime_pm;
> > + }
> > + }
> > +
> > ret = mipi_dsi_host_register(&dsi->base);
> > if (ret)
> > - goto err_disable_runtime_pm;
> > + goto err_deinit_platform;
> > clk_disable_unprepare(dsi->dsi_p_clk);
> > return 0;
> > +err_deinit_platform:
> > + if (dsi->platform_ops && dsi->platform_ops->exit)
> > + dsi->platform_ops->exit(dsi);
> > +
> > err_disable_runtime_pm:
> > pm_runtime_disable(&pdev->dev);
> > @@ -857,6 +883,10 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
> > struct cdns_dsi *dsi = platform_get_drvdata(pdev);
> > mipi_dsi_host_unregister(&dsi->base);
> > +
> > + if (dsi->platform_ops && dsi->platform_ops->exit)
> > + dsi->platform_ops->exit(dsi);
> > +
> > pm_runtime_disable(&pdev->dev);
> > return 0;
> > @@ -864,6 +894,11 @@ static int cdns_dsi_drm_remove(struct platform_device *pdev)
> > static const struct of_device_id cdns_dsi_of_match[] = {
> > { .compatible = "cdns,dsi" },
> > +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> > + { .compatible = "ti,j721e-dsi",
> > + .data = &dsi_ti_j721e_ops,
> > + },
>
> I find the above formatting a bit odd. I think this should do fine:
>
> { .compatible = "ti,j721e-dsi", .data = &dsi_ti_j721e_ops, },
>
> If you want multi-line, then I think the opening { should be on its own
> line, similarly to the closing }.
>
> > +#endif
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> > index 65cc77f19b39..37568b547fbe 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
> > @@ -439,9 +439,22 @@ struct cdns_dsi_input {
> > struct drm_bridge bridge;
> > };
> > +struct cdns_dsi;
> > +
> > +struct dsi_platform_ops {
> > + int (*init)(struct cdns_dsi *dsi);
> > + void (*exit)(struct cdns_dsi *dsi);
>
> I don't think init and exit are the opposites, but rather init and
> deinit/uninit.
>
> > + void (*enable)(struct cdns_dsi *dsi);
> > + void (*disable)(struct cdns_dsi *dsi);
> > +};
> > +
> > struct cdns_dsi {
> > struct mipi_dsi_host base;
> > void __iomem *regs;
> > +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> > + void __iomem *j721e_regs;
> > +#endif
> > + const struct dsi_platform_ops *platform_ops;
> > struct cdns_dsi_input input;
> > struct cdns_dsi_output output;
> > unsigned int direct_cmd_fifo_depth;
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> > new file mode 100644
> > index 000000000000..b5216acb333e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * TI j721e Cadence DSI wrapper
> > + *
> > + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
> > + * Author: Rahul T R <r-ravikumar@ti.com>
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "cdns-dsi-j721e.h"
> > +
> > +#define DSI_WRAP_REVISION 0x0
> > +#define DSI_WRAP_DPI_CONTROL 0x4
> > +#define DSI_WRAP_DSC_CONTROL 0x8
> > +#define DSI_WRAP_DPI_SECURE 0xc
> > +#define DSI_WRAP_DSI_0_ASF_STATUS 0x10
> > +
> > +#define DSI_WRAP_DPI_0_EN BIT(0)
> > +#define DSI_WRAP_DSI2_MUX_SEL BIT(4)
> > +
> > +static int cdns_dsi_j721e_init(struct cdns_dsi *dsi)
> > +{
> > + struct platform_device *pdev = to_platform_device(dsi->base.dev);
> > +
> > + dsi->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
> > + return PTR_ERR_OR_ZERO(dsi->j721e_regs);
> > +}
> > +
> > +static void cdns_dsi_j721e_enable(struct cdns_dsi *dsi)
> > +{
> > + /*
> > + * Enable DPI0 as its input. DSS0 DPI2 is connected
> > + * to DSI DPI0. This is the only supported configuration on
> > + * J721E.
> > + */
> > + writel(DSI_WRAP_DPI_0_EN, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
> > +}
> > +
> > +static void cdns_dsi_j721e_disable(struct cdns_dsi *dsi)
> > +{
> > + /* Put everything to defaults */
> > + writel(0, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
> > +}
> > +
> > +const struct dsi_platform_ops dsi_ti_j721e_ops = {
> > + .init = cdns_dsi_j721e_init,
> > + .enable = cdns_dsi_j721e_enable,
> > + .disable = cdns_dsi_j721e_disable,
> > +};
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> > new file mode 100644
> > index 000000000000..01f3dbd92db2
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * TI j721e Cadence DSI wrapper
> > + *
> > + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
> > + * Author: Rahul T R <r-ravikumar@ti.com>
> > + */
> > +
> > +#ifndef CDNS_DSI_J721E_H
> > +#define CDNS_DSI_J721E_H
> > +
> > +#include "cdns-dsi-core.h"
> > +
> > +struct dsi_platform_ops;
>
> You don't need the above line as you already include the cdns-dsi-core.h
>
Thanks for the detailed review
I have addressed the review comments
and sent a v9 of this series
Regards
Rahul T R
> > +extern const struct dsi_platform_ops dsi_ti_j721e_ops;
> > +
> > +#endif /* !CDNS_DSI_J721E_H */
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-31 12:24 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-21 17:18 [PATCH v8 0/5] Add support for CDNS DSI J721E wrapper Rahul T R
2022-10-21 17:18 ` [PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml Rahul T R
2022-10-21 17:18 ` [PATCH v8 2/5] dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on j721e Rahul T R
2022-10-21 17:18 ` [PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence Rahul T R
2022-10-26 6:15 ` Tomi Valkeinen
2022-10-21 17:18 ` [PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file Rahul T R
2022-10-26 6:16 ` Tomi Valkeinen
2022-10-21 17:18 ` [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper Rahul T R
2022-10-26 6:12 ` Tomi Valkeinen
2022-10-31 12:24 ` Rahul T R
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).