[PATCH v2 0/2] clk: renesas: RZ/G2L: Add support for no PM clocks

[PATCH v2 0/2] clk: renesas: RZ/G2L: Add support for no PM clocks

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds support for indicating MOD clocks as no PM
(if any). SoCs indicate no PM clocks by adding to no_pm_mod_clks[]
array.

Note this patch applies on top of [0] (rebased on renesas-clk-for-v6.2
branch).

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221026012123.159790-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

v1 -> v2
* Dropped DEF_NO_PM() macro
* Added genpd member to struct rzg2l_cpg_priv
* Added no_pm_mod_clks and num_no_pm_mod_clks members
  to struct rzg2l_cpg_info
* Updated commit messages

RFC->v1
* Added no_pm_mod_clks and num_no_pm_mod_clks members as part of
  struct rzg2l_cpg_priv so that we dont loop the entire mod clocks
  array for each device probe.
* Patch#2 unchanged

RFC: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220927203044.751611-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list

 drivers/clk/renesas/r9a07g044-cpg.c | 13 ++++++++++
 drivers/clk/renesas/rzg2l-cpg.c     | 37 ++++++++++++++++++-----------
 drivers/clk/renesas/rzg2l-cpg.h     |  4 ++++
 3 files changed, 40 insertions(+), 14 deletions(-)

-- 
2.25.1

[PATCH v2 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

There are cases where not all CPG_MOD clocks should be assumed to support
PM. For example on the CRU block there is a particular sequence that needs
to be followed to initialize the CSI-2 D-PHY in which individual clocks
need to be turned ON/OFF, due to which Runtime PM support wasn't used by
the CRU CSI-2 driver.

This patch adds support to allow indicating if PM is not supported by the
CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are
added to struct rzg2l_cpg_info so that MOD clocks which do not support PM
can be passed by no_pm_mod_clks[] array and when the driver uses Runtime
PM support the clk ID is matched against the no_pm_mod_clks[] array to see
if the clk is needed to be included as part of Runtime PM.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* Dropped DEF_NO_PM() macro
* Added genpd member to struct rzg2l_cpg_priv
* Added no_pm_mod_clks and num_no_pm_mod_clks members
  to struct rzg2l_cpg_info
* Updated commit message

RFC->v1
* Added no_pm_mod_clks and num_no_pm_mod_clks members as part of
  struct rzg2l_cpg_priv
---
 drivers/clk/renesas/rzg2l-cpg.c | 37 ++++++++++++++++++++-------------
 drivers/clk/renesas/rzg2l-cpg.h |  4 ++++
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index dfd676310ce9..66b909f31c77 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -95,6 +95,7 @@ struct rzg2l_pll5_mux_dsi_div_param {
  * @num_resets: Number of Module Resets in info->resets[]
  * @last_dt_core_clk: ID of the last Core Clock exported to DT
  * @info: Pointer to platform data
+ * @genpd: PM domain
  * @mux_dsi_div_params: pll5 mux and dsi div parameters
  */
 struct rzg2l_cpg_priv {
@@ -111,6 +112,8 @@ struct rzg2l_cpg_priv {
 
 	const struct rzg2l_cpg_info *info;
 
+	struct generic_pm_domain genpd;
+
 	struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
 };
 
@@ -1223,22 +1226,31 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
 	return devm_reset_controller_register(priv->dev, &priv->rcdev);
 }
 
-static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
+static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
+				const struct of_phandle_args *clkspec)
 {
+	const struct rzg2l_cpg_info *info = priv->info;
+	unsigned int id;
+	unsigned int i;
+
 	if (clkspec->args_count != 2)
 		return false;
 
-	switch (clkspec->args[0]) {
-	case CPG_MOD:
-		return true;
-
-	default:
+	if (clkspec->args[0] != CPG_MOD)
 		return false;
+
+	id = clkspec->args[1] + info->num_total_core_clks;
+	for (i = 0; i < info->num_no_pm_mod_clks; i++) {
+		if (info->no_pm_mod_clks[i] == id)
+			return false;
 	}
+
+	return true;
 }
 
 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 {
+	struct rzg2l_cpg_priv *priv = container_of(unused, struct rzg2l_cpg_priv, genpd);
 	struct device_node *np = dev->of_node;
 	struct of_phandle_args clkspec;
 	bool once = true;
@@ -1248,7 +1260,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
 
 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 					   &clkspec)) {
-		if (rzg2l_cpg_is_pm_clk(&clkspec)) {
+		if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
 			if (once) {
 				once = false;
 				error = pm_clk_create(dev);
@@ -1298,16 +1310,13 @@ static void rzg2l_cpg_genpd_remove(void *data)
 	pm_genpd_remove(data);
 }
 
-static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
+static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
 {
+	struct device *dev = priv->dev;
 	struct device_node *np = dev->of_node;
-	struct generic_pm_domain *genpd;
+	struct generic_pm_domain *genpd = &priv->genpd;
 	int ret;
 
-	genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
-	if (!genpd)
-		return -ENOMEM;
-
 	genpd->name = np->name;
 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
 		       GENPD_FLAG_ACTIVE_WAKEUP;
@@ -1377,7 +1386,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
 	if (error)
 		return error;
 
-	error = rzg2l_cpg_add_clk_domain(dev);
+	error = rzg2l_cpg_add_clk_domain(priv);
 	if (error)
 		return error;
 
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index cecbdf5e4f93..eee780276a9e 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -256,6 +256,10 @@ struct rzg2l_cpg_info {
 	unsigned int num_mod_clks;
 	unsigned int num_hw_mod_clks;
 
+	/* No PM Module Clocks */
+	const unsigned int *no_pm_mod_clks;
+	unsigned int num_no_pm_mod_clks;
+
 	/* Resets */
 	const struct rzg2l_reset *resets;
 	unsigned int num_resets;
-- 
2.25.1

[PATCH v2 2/2] clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g044_no_pm_mod_clks[] array.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* Dropped usage of DEF_NO_PM() macro
* Added CRU_SYSCLK and CRU_VCLK to no PM list
* Updated commit message

RFC->v1
* No change
---
 drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f5550fccb029..f923b7b3cfca 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
+static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {
+	MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
+	MOD_CLK_BASE + R9A07G044_CRU_VCLK,
+};
+
 #ifdef CONFIG_CLK_R9A07G044
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	/* Core Clocks */
@@ -429,6 +434,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	.num_mod_clks = ARRAY_SIZE(mod_clks.common),
 	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 
+	/* No PM Module Clocks */
+	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
@@ -454,6 +463,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 	.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
 	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
 
+	/* No PM Module Clocks */
+	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
-- 
2.25.1

Re: [PATCH v2 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> There are cases where not all CPG_MOD clocks should be assumed to support
> PM. For example on the CRU block there is a particular sequence that needs
> to be followed to initialize the CSI-2 D-PHY in which individual clocks
> need to be turned ON/OFF, due to which Runtime PM support wasn't used by
> the CRU CSI-2 driver.
>
> This patch adds support to allow indicating if PM is not supported by the
> CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are
> added to struct rzg2l_cpg_info so that MOD clocks which do not support PM
> can be passed by no_pm_mod_clks[] array and when the driver uses Runtime
> PM support the clk ID is matched against the no_pm_mod_clks[] array to see
> if the clk is needed to be included as part of Runtime PM.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * Dropped DEF_NO_PM() macro
> * Added genpd member to struct rzg2l_cpg_priv
> * Added no_pm_mod_clks and num_no_pm_mod_clks members
>   to struct rzg2l_cpg_info
> * Updated commit message

Thanks for the update!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c

>
>  static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)

Time to rename "unused" to "domain" ;-)

>  {
> +       struct rzg2l_cpg_priv *priv = container_of(unused, struct rzg2l_cpg_priv, genpd);

I can fix that while applying...

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/2] clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
> sequence for the CRU block hence add these clocks to
> r9a07g044_no_pm_mod_clks[] array.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * Dropped usage of DEF_NO_PM() macro
> * Added CRU_SYSCLK and CRU_VCLK to no PM list
> * Updated commit message

Thanks for the update!

> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
>         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
>  };
>
> +static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {

This cannot be __initconst, so please drop this keyword.

> +       MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
> +       MOD_CLK_BASE + R9A07G044_CRU_VCLK,
> +};

I believe I haven't seen patches yet to add support for these clocks?
Perhaps these can be combined?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM

[Lad, Prabhakar]

HI Geert,

Thank you for the review.

On Wed, Oct 26, 2022 at 8:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > There are cases where not all CPG_MOD clocks should be assumed to support
> > PM. For example on the CRU block there is a particular sequence that needs
> > to be followed to initialize the CSI-2 D-PHY in which individual clocks
> > need to be turned ON/OFF, due to which Runtime PM support wasn't used by
> > the CRU CSI-2 driver.
> >
> > This patch adds support to allow indicating if PM is not supported by the
> > CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are
> > added to struct rzg2l_cpg_info so that MOD clocks which do not support PM
> > can be passed by no_pm_mod_clks[] array and when the driver uses Runtime
> > PM support the clk ID is matched against the no_pm_mod_clks[] array to see
> > if the clk is needed to be included as part of Runtime PM.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped DEF_NO_PM() macro
> > * Added genpd member to struct rzg2l_cpg_priv
> > * Added no_pm_mod_clks and num_no_pm_mod_clks members
> >   to struct rzg2l_cpg_info
> > * Updated commit message
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
>
> >
> >  static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
>
> Time to rename "unused" to "domain" ;-)
>
Indeed, I think the naming came from R-Car :)

> >  {
> > +       struct rzg2l_cpg_priv *priv = container_of(unused, struct rzg2l_cpg_priv, genpd);
>
> I can fix that while applying...
>
Thanks.

> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>

Cheers,
Prabhakar

Re: [PATCH v2 2/2] clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list

[Lad, Prabhakar]

Hi Geert,

THank you for the review.

On Wed, Oct 26, 2022 at 8:58 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
> > sequence for the CRU block hence add these clocks to
> > r9a07g044_no_pm_mod_clks[] array.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped usage of DEF_NO_PM() macro
> > * Added CRU_SYSCLK and CRU_VCLK to no PM list
> > * Updated commit message
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
> >         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
> >  };
> >
> > +static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {
>
> This cannot be __initconst, so please drop this keyword.
>
OK.

> > +       MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
> > +       MOD_CLK_BASE + R9A07G044_CRU_VCLK,
> > +};
>
> I believe I haven't seen patches yet to add support for these clocks?
> Perhaps these can be combined?
>
Ahh my bad, yes the patches have not been sent out for it, I'll
combine this while adding the clocks.

Cheers,
Prabhakar