* [PATCH 09/20] arm64: dts: Update cache properties for lg
@ 2022-10-31 9:20 Pierre Gondois
0 siblings, 0 replies; only message in thread
From: Pierre Gondois @ 2022-10-31 9:20 UTC (permalink / raw)
To: linux-kernel
Cc: pierre.gondois, Rob.Herring, Chanho Min, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel, devicetree
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..25ed9aeee2dc 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..db82fd4cc759 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,7 @@ cpu3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
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