* [PATCH 18/20] arm64: dts: Update cache properties for rockchip
@ 2022-10-31 9:21 Pierre Gondois
0 siblings, 0 replies; only message in thread
From: Pierre Gondois @ 2022-10-31 9:21 UTC (permalink / raw)
To: linux-kernel
Cc: pierre.gondois, Rob.Herring, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Johan Jonker, Christopher Obbard,
Ezequiel Garcia, devicetree, linux-arm-kernel, linux-rockchip
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 2dfa67f1cd67..dd228a256a32 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -96,6 +96,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 49ae15708a0b..8741914cea44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -102,6 +102,7 @@ CPU_SLEEP: cpu-sleep {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
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