* [PATCH] x86/resctrl: Move MSR defines into msr-index.h
@ 2022-11-06 21:29 Borislav Petkov
2022-11-08 22:59 ` Reinette Chatre
2022-11-27 22:09 ` [tip: x86/cache] " tip-bot2 for Borislav Petkov
0 siblings, 2 replies; 4+ messages in thread
From: Borislav Petkov @ 2022-11-06 21:29 UTC (permalink / raw)
To: Fenghua Yu, Reinette Chatre, Babu Moger; +Cc: X86 ML, LKML
From: Borislav Petkov <bp@suse.de>
msr-index.h should contain all MSRs for easier grepping for MSR numbers
when dealing with unchecked MSR access warnings, for example.
Move the resctrl ones. Prefix IA32_PQR_ASSOC with "MSR_" while at it.
No functional changes.
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/msr-index.h | 22 ++++++++++++++++------
arch/x86/include/asm/resctrl.h | 8 +++-----
arch/x86/kernel/cpu/resctrl/core.c | 2 +-
arch/x86/kernel/cpu/resctrl/internal.h | 10 +---------
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
5 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index a3eb4d3e70b8..c29cf6d1935b 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -4,12 +4,7 @@
#include <linux/bits.h>
-/*
- * CPU model specific register (MSR) numbers.
- *
- * Do not add new entries to this file unless the definitions are shared
- * between multiple compilation units.
- */
+/* CPU model specific register (MSR) numbers. */
/* x86-64 specific MSRs */
#define MSR_EFER 0xc0000080 /* extended feature register */
@@ -1051,6 +1046,21 @@
#define VMX_BASIC_MEM_TYPE_WB 6LLU
#define VMX_BASIC_INOUT 0x0040000000000000LLU
+/* Resctrl MSRs: */
+/* - Intel: */
+#define MSR_IA32_L3_QOS_CFG 0xc81
+#define MSR_IA32_L2_QOS_CFG 0xc82
+#define MSR_IA32_QM_EVTSEL 0xc8d
+#define MSR_IA32_QM_CTR 0xc8e
+#define MSR_IA32_PQR_ASSOC 0xc8f
+#define MSR_IA32_L3_CBM_BASE 0xc90
+#define MSR_IA32_L2_CBM_BASE 0xd10
+#define MSR_IA32_MBA_THRTL_BASE 0xd50
+
+
+/* - AMD: */
+#define MSR_IA32_MBA_BW_BASE 0xc0000200
+
/* MSR_IA32_VMX_MISC bits */
#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
index d24b04ebf950..52788f79786f 100644
--- a/arch/x86/include/asm/resctrl.h
+++ b/arch/x86/include/asm/resctrl.h
@@ -7,8 +7,6 @@
#include <linux/sched.h>
#include <linux/jump_label.h>
-#define IA32_PQR_ASSOC 0x0c8f
-
/**
* struct resctrl_pqr_state - State cache for the PQR MSR
* @cur_rmid: The cached Resource Monitoring ID
@@ -16,8 +14,8 @@
* @default_rmid: The user assigned Resource Monitoring ID
* @default_closid: The user assigned cached Class Of Service ID
*
- * The upper 32 bits of IA32_PQR_ASSOC contain closid and the
- * lower 10 bits rmid. The update to IA32_PQR_ASSOC always
+ * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
+ * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
* contains both parts, so we need to cache them. This also
* stores the user configured per cpu CLOSID and RMID.
*
@@ -77,7 +75,7 @@ static void __resctrl_sched_in(void)
if (closid != state->cur_closid || rmid != state->cur_rmid) {
state->cur_closid = closid;
state->cur_rmid = rmid;
- wrmsr(IA32_PQR_ASSOC, rmid, closid);
+ wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
}
}
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 03cfbf0fe000..c98e52ff5f20 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -575,7 +575,7 @@ static void clear_closid_rmid(int cpu)
state->default_rmid = 0;
state->cur_closid = 0;
state->cur_rmid = 0;
- wrmsr(IA32_PQR_ASSOC, 0, 0);
+ wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
}
static int resctrl_online_cpu(unsigned int cpu)
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 5f7128686cfd..4f43da46243d 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -8,15 +8,7 @@
#include <linux/fs_context.h>
#include <linux/jump_label.h>
-#define MSR_IA32_L3_QOS_CFG 0xc81
-#define MSR_IA32_L2_QOS_CFG 0xc82
-#define MSR_IA32_L3_CBM_BASE 0xc90
-#define MSR_IA32_L2_CBM_BASE 0xd10
-#define MSR_IA32_MBA_THRTL_BASE 0xd50
-#define MSR_IA32_MBA_BW_BASE 0xc0000200
-
-#define MSR_IA32_QM_CTR 0x0c8e
-#define MSR_IA32_QM_EVTSEL 0x0c8d
+
#define L3_QOS_CDP_ENABLE 0x01ULL
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index d961ae3ed96e..ba8d0763b36b 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -477,7 +477,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
* pseudo-locked followed by reading of kernel memory to load it
* into the cache.
*/
- __wrmsr(IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
+ __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
/*
* Cache was flushed earlier. Now access kernel memory to read it
* into cache region associated with just activated plr->closid.
@@ -513,7 +513,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
* Critical section end: restore closid with capacity bitmask that
* does not overlap with pseudo-locked region.
*/
- __wrmsr(IA32_PQR_ASSOC, rmid_p, closid_p);
+ __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
/* Re-enable the hardware prefetcher(s) */
wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr);
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] x86/resctrl: Move MSR defines into msr-index.h
2022-11-06 21:29 [PATCH] x86/resctrl: Move MSR defines into msr-index.h Borislav Petkov
@ 2022-11-08 22:59 ` Reinette Chatre
2022-11-08 23:14 ` Borislav Petkov
2022-11-27 22:09 ` [tip: x86/cache] " tip-bot2 for Borislav Petkov
1 sibling, 1 reply; 4+ messages in thread
From: Reinette Chatre @ 2022-11-08 22:59 UTC (permalink / raw)
To: Borislav Petkov, Fenghua Yu, Babu Moger; +Cc: X86 ML, LKML
Hi Boris,
On 11/6/2022 1:29 PM, Borislav Petkov wrote:
> From: Borislav Petkov <bp@suse.de>
>
> msr-index.h should contain all MSRs for easier grepping for MSR numbers
> when dealing with unchecked MSR access warnings, for example.
>
> Move the resctrl ones. Prefix IA32_PQR_ASSOC with "MSR_" while at it.
>
> No functional changes.
>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> ---
> arch/x86/include/asm/msr-index.h | 22 ++++++++++++++++------
> arch/x86/include/asm/resctrl.h | 8 +++-----
> arch/x86/kernel/cpu/resctrl/core.c | 2 +-
> arch/x86/kernel/cpu/resctrl/internal.h | 10 +---------
> arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
> 5 files changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index a3eb4d3e70b8..c29cf6d1935b 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -4,12 +4,7 @@
>
> #include <linux/bits.h>
>
> -/*
> - * CPU model specific register (MSR) numbers.
> - *
> - * Do not add new entries to this file unless the definitions are shared
> - * between multiple compilation units.
> - */
> +/* CPU model specific register (MSR) numbers. */
>
Not an objection, just an observation: the above is a significant
change for a patch with the x86/resctrl prefix.
> /* x86-64 specific MSRs */
> #define MSR_EFER 0xc0000080 /* extended feature register */
> @@ -1051,6 +1046,21 @@
> #define VMX_BASIC_MEM_TYPE_WB 6LLU
> #define VMX_BASIC_INOUT 0x0040000000000000LLU
>
> +/* Resctrl MSRs: */
> +/* - Intel: */
> +#define MSR_IA32_L3_QOS_CFG 0xc81
> +#define MSR_IA32_L2_QOS_CFG 0xc82
> +#define MSR_IA32_QM_EVTSEL 0xc8d
> +#define MSR_IA32_QM_CTR 0xc8e
> +#define MSR_IA32_PQR_ASSOC 0xc8f
> +#define MSR_IA32_L3_CBM_BASE 0xc90
> +#define MSR_IA32_L2_CBM_BASE 0xd10
> +#define MSR_IA32_MBA_THRTL_BASE 0xd50
> +
> +
> +/* - AMD: */
> +#define MSR_IA32_MBA_BW_BASE 0xc0000200
> +
Is it important to distinguish between Intel and AMD?
All but one (MSR_IA32_MBA_THRTL_BASE) of the register values
under the "Intel" heading are also used by AMD.
(sidenote: multiple blank lines above)
> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
> index 5f7128686cfd..4f43da46243d 100644
> --- a/arch/x86/kernel/cpu/resctrl/internal.h
> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
> @@ -8,15 +8,7 @@
> #include <linux/fs_context.h>
> #include <linux/jump_label.h>
>
> -#define MSR_IA32_L3_QOS_CFG 0xc81
> -#define MSR_IA32_L2_QOS_CFG 0xc82
> -#define MSR_IA32_L3_CBM_BASE 0xc90
> -#define MSR_IA32_L2_CBM_BASE 0xd10
> -#define MSR_IA32_MBA_THRTL_BASE 0xd50
> -#define MSR_IA32_MBA_BW_BASE 0xc0000200
> -
> -#define MSR_IA32_QM_CTR 0x0c8e
> -#define MSR_IA32_QM_EVTSEL 0x0c8d
> +
>
> #define L3_QOS_CDP_ENABLE 0x01ULL
This new empty line results in a multiple blank lines
warning in this area.
Reinette
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86/resctrl: Move MSR defines into msr-index.h
2022-11-08 22:59 ` Reinette Chatre
@ 2022-11-08 23:14 ` Borislav Petkov
0 siblings, 0 replies; 4+ messages in thread
From: Borislav Petkov @ 2022-11-08 23:14 UTC (permalink / raw)
To: Reinette Chatre; +Cc: Fenghua Yu, Babu Moger, X86 ML, LKML
On Tue, Nov 08, 2022 at 02:59:12PM -0800, Reinette Chatre wrote:
> Not an objection, just an observation: the above is a significant
> change for a patch with the x86/resctrl prefix.
Yeah, I felt it is a small-enough change not to warrant a separate
patch.
> Is it important to distinguish between Intel and AMD?
Yeah, look at the rest of that file.
> All but one (MSR_IA32_MBA_THRTL_BASE) of the register values
> under the "Intel" heading are also used by AMD.
This basically says that AMD is using Intel's MSRs. Which is fine.
I'll fix the multiple blank lines.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply [flat|nested] 4+ messages in thread
* [tip: x86/cache] x86/resctrl: Move MSR defines into msr-index.h
2022-11-06 21:29 [PATCH] x86/resctrl: Move MSR defines into msr-index.h Borislav Petkov
2022-11-08 22:59 ` Reinette Chatre
@ 2022-11-27 22:09 ` tip-bot2 for Borislav Petkov
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot2 for Borislav Petkov @ 2022-11-27 22:09 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Borislav Petkov, x86, linux-kernel
The following commit has been merged into the x86/cache branch of tip:
Commit-ID: 97fa21f65c3eb5bbab9b4734bed37fd624cddd86
Gitweb: https://git.kernel.org/tip/97fa21f65c3eb5bbab9b4734bed37fd624cddd86
Author: Borislav Petkov <bp@suse.de>
AuthorDate: Sun, 06 Nov 2022 22:24:08 +01:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Sun, 27 Nov 2022 23:00:45 +01:00
x86/resctrl: Move MSR defines into msr-index.h
msr-index.h should contain all MSRs for easier grepping for MSR numbers
when dealing with unchecked MSR access warnings, for example.
Move the resctrl ones. Prefix IA32_PQR_ASSOC with "MSR_" while at it.
No functional changes.
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20221106212923.20699-1-bp@alien8.de
---
arch/x86/include/asm/msr-index.h | 21 +++++++++++++++------
arch/x86/include/asm/resctrl.h | 8 +++-----
arch/x86/kernel/cpu/resctrl/core.c | 2 +-
arch/x86/kernel/cpu/resctrl/internal.h | 10 ----------
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
5 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 10ac527..9308eb9 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -4,12 +4,7 @@
#include <linux/bits.h>
-/*
- * CPU model specific register (MSR) numbers.
- *
- * Do not add new entries to this file unless the definitions are shared
- * between multiple compilation units.
- */
+/* CPU model specific register (MSR) numbers. */
/* x86-64 specific MSRs */
#define MSR_EFER 0xc0000080 /* extended feature register */
@@ -1050,6 +1045,20 @@
#define VMX_BASIC_MEM_TYPE_WB 6LLU
#define VMX_BASIC_INOUT 0x0040000000000000LLU
+/* Resctrl MSRs: */
+/* - Intel: */
+#define MSR_IA32_L3_QOS_CFG 0xc81
+#define MSR_IA32_L2_QOS_CFG 0xc82
+#define MSR_IA32_QM_EVTSEL 0xc8d
+#define MSR_IA32_QM_CTR 0xc8e
+#define MSR_IA32_PQR_ASSOC 0xc8f
+#define MSR_IA32_L3_CBM_BASE 0xc90
+#define MSR_IA32_L2_CBM_BASE 0xd10
+#define MSR_IA32_MBA_THRTL_BASE 0xd50
+
+/* - AMD: */
+#define MSR_IA32_MBA_BW_BASE 0xc0000200
+
/* MSR_IA32_VMX_MISC bits */
#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
index d24b04e..52788f7 100644
--- a/arch/x86/include/asm/resctrl.h
+++ b/arch/x86/include/asm/resctrl.h
@@ -7,8 +7,6 @@
#include <linux/sched.h>
#include <linux/jump_label.h>
-#define IA32_PQR_ASSOC 0x0c8f
-
/**
* struct resctrl_pqr_state - State cache for the PQR MSR
* @cur_rmid: The cached Resource Monitoring ID
@@ -16,8 +14,8 @@
* @default_rmid: The user assigned Resource Monitoring ID
* @default_closid: The user assigned cached Class Of Service ID
*
- * The upper 32 bits of IA32_PQR_ASSOC contain closid and the
- * lower 10 bits rmid. The update to IA32_PQR_ASSOC always
+ * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
+ * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
* contains both parts, so we need to cache them. This also
* stores the user configured per cpu CLOSID and RMID.
*
@@ -77,7 +75,7 @@ static void __resctrl_sched_in(void)
if (closid != state->cur_closid || rmid != state->cur_rmid) {
state->cur_closid = closid;
state->cur_rmid = rmid;
- wrmsr(IA32_PQR_ASSOC, rmid, closid);
+ wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
}
}
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 03cfbf0..c98e52f 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -575,7 +575,7 @@ static void clear_closid_rmid(int cpu)
state->default_rmid = 0;
state->cur_closid = 0;
state->cur_rmid = 0;
- wrmsr(IA32_PQR_ASSOC, 0, 0);
+ wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
}
static int resctrl_online_cpu(unsigned int cpu)
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 5f71286..5ebd28e 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -8,16 +8,6 @@
#include <linux/fs_context.h>
#include <linux/jump_label.h>
-#define MSR_IA32_L3_QOS_CFG 0xc81
-#define MSR_IA32_L2_QOS_CFG 0xc82
-#define MSR_IA32_L3_CBM_BASE 0xc90
-#define MSR_IA32_L2_CBM_BASE 0xd10
-#define MSR_IA32_MBA_THRTL_BASE 0xd50
-#define MSR_IA32_MBA_BW_BASE 0xc0000200
-
-#define MSR_IA32_QM_CTR 0x0c8e
-#define MSR_IA32_QM_EVTSEL 0x0c8d
-
#define L3_QOS_CDP_ENABLE 0x01ULL
#define L2_QOS_CDP_ENABLE 0x01ULL
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index d961ae3..ba8d076 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -477,7 +477,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
* pseudo-locked followed by reading of kernel memory to load it
* into the cache.
*/
- __wrmsr(IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
+ __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
/*
* Cache was flushed earlier. Now access kernel memory to read it
* into cache region associated with just activated plr->closid.
@@ -513,7 +513,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
* Critical section end: restore closid with capacity bitmask that
* does not overlap with pseudo-locked region.
*/
- __wrmsr(IA32_PQR_ASSOC, rmid_p, closid_p);
+ __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
/* Re-enable the hardware prefetcher(s) */
wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr);
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-11-27 22:09 UTC | newest]
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2022-11-06 21:29 [PATCH] x86/resctrl: Move MSR defines into msr-index.h Borislav Petkov
2022-11-08 22:59 ` Reinette Chatre
2022-11-08 23:14 ` Borislav Petkov
2022-11-27 22:09 ` [tip: x86/cache] " tip-bot2 for Borislav Petkov
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