[PATCH 1/3] media: dt-bindings: media: mediatek: vcodec: Fix clock num not correctly

[PATCH 1/3] media: dt-bindings: media: mediatek: vcodec: Fix clock num not correctly

[Yunfei Dong]

mt8195 and mt8192 have different clock numbers, can't write 'clocks' and
'clock-names' with const value.

Move 'assigned-clocks' and 'assigned-clock-parents' to parent node.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
 .../media/mediatek,vcodec-subdev-decoder.yaml | 119 +++++++++++-------
 1 file changed, 72 insertions(+), 47 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index c4f20acdc1f8..794012853834 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -89,23 +89,33 @@ properties:
 
   ranges: true
 
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
 # Required child node:
 patternProperties:
-  '^vcodec-lat@[0-9a-f]+$':
+  '^vcodec-lat-soc@[0-9a-f]+$':
     type: object
 
     properties:
       compatible:
         enum:
-          - mediatek,mtk-vcodec-lat
           - mediatek,mtk-vcodec-lat-soc
 
       reg:
         maxItems: 1
 
-      interrupts:
-        maxItems: 1
-
       iommus:
         minItems: 1
         maxItems: 32
@@ -114,22 +124,55 @@ patternProperties:
           Refer to bindings/iommu/mediatek,iommu.yaml.
 
       clocks:
+        minItems: 1
         maxItems: 5
 
       clock-names:
-        items:
-          - const: sel
-          - const: soc-vdec
-          - const: soc-lat
-          - const: vdec
-          - const: top
+        minItems: 1
+        maxItems: 5
 
-      assigned-clocks:
+      power-domains:
         maxItems: 1
 
-      assigned-clock-parents:
+    required:
+      - compatible
+      - reg
+      - iommus
+      - clocks
+      - clock-names
+      - power-domains
+
+    additionalProperties: false
+
+  '^vcodec-lat@[0-9a-f]+$':
+    type: object
+
+    properties:
+      compatible:
+        enum:
+          - mediatek,mtk-vcodec-lat
+
+      reg:
+        maxItems: 1
+
+      interrupts:
         maxItems: 1
 
+      iommus:
+        minItems: 1
+        maxItems: 32
+        description: |
+          List of the hardware port in respective IOMMU block for current Socs.
+          Refer to bindings/iommu/mediatek,iommu.yaml.
+
+      clocks:
+        minItems: 1
+        maxItems: 5
+
+      clock-names:
+        minItems: 1
+        maxItems: 5
+
       power-domains:
         maxItems: 1
 
@@ -139,8 +182,6 @@ patternProperties:
       - iommus
       - clocks
       - clock-names
-      - assigned-clocks
-      - assigned-clock-parents
       - power-domains
 
     additionalProperties: false
@@ -166,15 +207,12 @@ patternProperties:
           Refer to bindings/iommu/mediatek,iommu.yaml.
 
       clocks:
+        minItems: 1
         maxItems: 5
 
       clock-names:
-        items:
-          - const: sel
-          - const: soc-vdec
-          - const: soc-lat
-          - const: vdec
-          - const: top
+        minItems: 1
+        maxItems: 5
 
       assigned-clocks:
         maxItems: 1
@@ -188,12 +226,9 @@ patternProperties:
     required:
       - compatible
       - reg
-      - interrupts
       - iommus
       - clocks
       - clock-names
-      - assigned-clocks
-      - assigned-clock-parents
       - power-domains
 
     additionalProperties: false
@@ -205,17 +240,10 @@ required:
   - mediatek,scp
   - dma-ranges
   - ranges
-
-if:
-  properties:
-    compatible:
-      contains:
-        enum:
-          - mediatek,mtk-vcodec-lat
-
-then:
-  required:
-    - interrupts
+  - clocks
+  - clock-names
+  - assigned-clocks
+  - assigned-clock-parents
 
 additionalProperties: false
 
@@ -241,6 +269,11 @@ examples:
             #size-cells = <2>;
             ranges = <0 0 0 0x16000000 0 0x40000>;
             reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
+            clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+                <&topckgen CLK_TOP_MAINPLL_D4>;
+            clock-names = "sel", "top";
+            assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+            assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
             vcodec-lat@10000 {
                 compatible = "mediatek,mtk-vcodec-lat";
                 reg = <0 0x10000 0 0x800>;
@@ -253,14 +286,10 @@ examples:
                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
                     <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
-                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
-                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+                clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
                     <&vdecsys_soc CLK_VDEC_SOC_LAT>,
-                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
-                    <&topckgen CLK_TOP_MAINPLL_D4>;
+                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
                 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
-                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
-                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
                 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
             };
 
@@ -279,14 +308,10 @@ examples:
                     <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
                     <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
                     <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
-                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
-                    <&vdecsys CLK_VDEC_VDEC>,
+                clocks = <&vdecsys CLK_VDEC_VDEC>,
                     <&vdecsys CLK_VDEC_LAT>,
-                    <&vdecsys CLK_VDEC_LARB1>,
-                    <&topckgen CLK_TOP_MAINPLL_D4>;
+                    <&vdecsys CLK_VDEC_LARB1>;
                 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
-                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
-                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
                 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
             };
         };
-- 
2.18.0

[PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2

[Yunfei Dong]

Need to add racing control register base in device node for mt8195 support
inner racing mode. Changing the max reg value from 1 to 2.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
 .../bindings/media/mediatek,vcodec-subdev-decoder.yaml          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index 794012853834..1697feb1f854 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -61,7 +61,7 @@ properties:
       - mediatek,mt8195-vcodec-dec
 
   reg:
-    maxItems: 1
+    maxItems: 2
 
   iommus:
     minItems: 1
-- 
2.18.0

[PATCH 3/3] arm64: dts: mt8195: Add video decoder node

[Yunfei Dong]

Add video decoder node to mt8195 device tree.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
dtbs_check pass.
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 63 ++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..ffabf91d4273 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1874,6 +1874,69 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
 		};
 
+		video-codec@18000000 {
+			compatible = "mediatek,mt8195-vcodec-dec";
+			mediatek,scp = <&scp>;
+			iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			reg = <0 0x18000000 0 0x1000>,      /* VDEC_SYS */
+			      <0 0x18004000 0 0x1000>;      /* VDEC_RACING_CTRL */
+			ranges = <0 0 0 0x18000000 0 0x26000>;
+			clocks = <&topckgen CLK_TOP_VDEC>,
+			         <&topckgen CLK_TOP_UNIVPLL_D4>;
+			clock-names = "vdec-sel", "top";
+			assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+
+			vcodec-lat-soc@2000 {
+				compatible = "mediatek,mtk-vcodec-lat-soc";
+				reg = <0 0x2000 0 0x800>;		/* VDEC_MISC */
+				iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
+					 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
+				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
+				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+			};
+
+			vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0 0x10000 0 0x800>;		/* VDEC_MISC */
+				interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
+					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
+					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
+					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
+				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
+				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+			};
+
+			vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;		/* VDEC_CORE_MISC */
+				interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
+					 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
+				clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LAT>;
+				clock-names = "vdec-vdec", "vdec-lat";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			};
+		};
+
 		larb24: larb@1800d000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x1800d000 0 0x1000>;
-- 
2.18.0

Re: [PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2

[AngeloGioacchino Del Regno]

Il 09/11/22 08:35, Yunfei Dong ha scritto:
> Need to add racing control register base in device node for mt8195 support
> inner racing mode. Changing the max reg value from 1 to 2.
> 
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
>   .../bindings/media/mediatek,vcodec-subdev-decoder.yaml          | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> index 794012853834..1697feb1f854 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
> @@ -61,7 +61,7 @@ properties:
>         - mediatek,mt8195-vcodec-dec
>   
>     reg:
> -    maxItems: 1
> +    maxItems: 2

What about doing, instead...

- description: VDEC_SYS register space
- description: VDEC_RACING_CTRL register space

then, setting `minItems: 1` will make the racing_ctrl iospace optional :-)

Regards,
Angelo

Re: [PATCH 3/3] arm64: dts: mt8195: Add video decoder node

[AngeloGioacchino Del Regno]

Il 09/11/22 08:35, Yunfei Dong ha scritto:
> Add video decoder node to mt8195 device tree.
> 
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
> dtbs_check pass.
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 63 ++++++++++++++++++++++++
>   1 file changed, 63 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..ffabf91d4273 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1874,6 +1874,69 @@
>   			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
>   		};
>   
> +		video-codec@18000000 {
> +			compatible = "mediatek,mt8195-vcodec-dec";
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
> +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			reg = <0 0x18000000 0 0x1000>,      /* VDEC_SYS */
> +			      <0 0x18004000 0 0x1000>;      /* VDEC_RACING_CTRL */

Since we're adding register descriptions to the schema file, you don't need any
comments in front of the iospaces that you're declaring here... this means that
it also fits on one line:
			reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>;

> +			ranges = <0 0 0 0x18000000 0 0x26000>;
> +			clocks = <&topckgen CLK_TOP_VDEC>,
> +			         <&topckgen CLK_TOP_UNIVPLL_D4>;
> +			clock-names = "vdec-sel", "top";
> +			assigned-clocks = <&topckgen CLK_TOP_VDEC>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +
> +			vcodec-lat-soc@2000 {
> +				compatible = "mediatek,mtk-vcodec-lat-soc";
> +				reg = <0 0x2000 0 0x800>;		/* VDEC_MISC */

We can perhaps add descriptions to the schema file for VDEC_MISC as well,
meaning that we don't need that comment as well.

> +				iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
> +					 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
> +				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
> +				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
> +				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> +			};
> +
> +			vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0 0x10000 0 0x800>;		/* VDEC_MISC */

same here

> +				interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
> +				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
> +				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
> +				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> +			};
> +
> +			vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;		/* VDEC_CORE_MISC */

...and same here too.

Regards,
Angelo

Re: [PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2

[Rob Herring]

On Wed, 09 Nov 2022 15:35:28 +0800, Yunfei Dong wrote:
> Need to add racing control register base in device node for mt8195 support
> inner racing mode. Changing the max reg value from 1 to 2.
> 
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
>  .../bindings/media/mediatek,vcodec-subdev-decoder.yaml          | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.example.dtb: video-codec@16000000: reg: [[0, 369098752, 0, 4096]] is too short
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2

[Yunfei Dong (董云飞)]

Dear AngeloGioacchino Del,

Thank for your suggestion, looks very reasonable.
Fix in v2.

Best regards,
Yunfei Dong

On Wed, 2022-11-09 at 10:29 +0100, AngeloGioacchino Del Regno wrote:
> Il 09/11/22 08:35, Yunfei Dong ha scritto:
> > Need to add racing control register base in device node for mt8195
> > support
> > inner racing mode. Changing the max reg value from 1 to 2.
> > 
> > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> > ---
> >   .../bindings/media/mediatek,vcodec-subdev-decoder.yaml          | 
> > 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > decoder.yaml
> > index 794012853834..1697feb1f854 100644
> > --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > subdev-decoder.yaml
> > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > subdev-decoder.yaml
> > @@ -61,7 +61,7 @@ properties:
> >         - mediatek,mt8195-vcodec-dec
> >   
> >     reg:
> > -    maxItems: 1
> > +    maxItems: 2
> 
> What about doing, instead...
> 
> - description: VDEC_SYS register space
> - description: VDEC_RACING_CTRL register space
> 
> then, setting `minItems: 1` will make the racing_ctrl iospace
> optional :-)
> 
> Regards,
> Angelo
> 
> 

Re: [PATCH 2/3] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2

[Yunfei Dong (董云飞)]

Hi Rob,

Thanks for your comments, already fixed in patch v2.

Best Regards,
Yunfei Dong
On Wed, 2022-11-09 at 06:59 -0600, Rob Herring wrote:
> On Wed, 09 Nov 2022 15:35:28 +0800, Yunfei Dong wrote:
> > Need to add racing control register base in device node for mt8195
> > support
> > inner racing mode. Changing the max reg value from 1 to 2.
> > 
> > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> > ---
> >  .../bindings/media/mediatek,vcodec-subdev-decoder.yaml          |
> > 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-
> ci/linux/Documentation/devicetree/bindings/media/mediatek,vcodec-
> subdev-decoder.example.dtb: video-codec@16000000: reg: [[0,
> 369098752, 0, 4096]] is too short
> 	From schema: /builds/robherring/dt-review-
> ci/linux/Documentation/devicetree/bindings/media/mediatek,vcodec-
> subdev-decoder.yaml
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/patch/
> 
> This check can fail if there are any dependencies. The base for a
> patch
> series is generally the most recent rc1.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up
> to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit.
> 
>