[PATCH v4 0/4] Add dp-intf and dp nodes

[PATCH v4 0/4] Add dp-intf and dp nodes

[Bo-Chen Chen]

This series add MediaTek dp-intf nodes and dp nodes.
This series is based on linux-next-20220915.

Changes for v4:
1. Rebase to linux-next 20221109.

Changes for v3:
1. Update commit message for "arm64: dts: mediatek: cherry: Add edptx and dptx support".

Changes for v2:
1. Update commit messages.
2. reorder the place of "status = "disabled";"
3. reorder the place of dp-intf.

Bo-Chen Chen (4):
  arm64: dts: mt8195: Add dp-intf nodes
  arm64: dts: mt8195: Add edptx and dptx nodes
  arm64: dts: mediatek: cherry: Add dp-intf ports
  arm64: dts: mediatek: cherry: Add edptx and dptx support

 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 86 +++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 48 +++++++++++
 2 files changed, 134 insertions(+)

-- 
2.18.0

[PATCH v4 1/4] arm64: dts: mt8195: Add dp-intf nodes

[Bo-Chen Chen]

Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.

Dp-intf0 is for edptx and dp-intf1 is for dptx.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2edfc21ece56..c380738d10cb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2094,6 +2094,17 @@
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
 		};
 
+		dp_intf0: dp-intf@1c015000 {
+			compatible = "mediatek,mt8195-dp-intf";
+			reg = <0 0x1c015000 0 0x1000>;
+			interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
+				 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL1>;
+			clock-names = "engine", "pixel", "pll";
+			status = "disabled";
+		};
+
 		mutex: mutex@1c016000 {
 			compatible = "mediatek,mt8195-disp-mutex";
 			reg = <0 0x1c016000 0 0x1000>;
@@ -2182,5 +2193,17 @@
 			clock-names = "apb", "smi", "gals";
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
 		};
+
+		dp_intf1: dp-intf@1c113000 {
+			compatible = "mediatek,mt8195-dp-intf";
+			reg = <0 0x1c113000 0 0x1000>;
+			interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+			clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+				 <&vdosys1 CLK_VDO1_DPINTF>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL2>;
+			clock-names = "engine", "pixel", "pll";
+			status = "disabled";
+		};
 	};
 };
-- 
2.18.0

[PATCH v4 2/4] arm64: dts: mt8195: Add edptx and dptx nodes

[Bo-Chen Chen]

In MT8195, we use edptx as the internal display interface and use
dptx as the external display interface. Therefore, we need to add
these nodes to support the internal display and the external display.

- Add dp calibration data in the efuse node.
- Add edptx and dptx nodes for MT8195.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c380738d10cb..7acbef5a4517 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1244,6 +1244,9 @@
 				reg = <0x189 0x2>;
 				bits = <7 5>;
 			};
+			dp_calibration: dp-data@1ac {
+				reg = <0x1ac 0x10>;
+			};
 		};
 
 		u3phy2: t-phy@11c40000 {
@@ -2205,5 +2208,27 @@
 			clock-names = "engine", "pixel", "pll";
 			status = "disabled";
 		};
+
+		edp_tx: edp-tx@1c500000 {
+			compatible = "mediatek,mt8195-edp-tx";
+			reg = <0 0x1c500000 0 0x8000>;
+			nvmem-cells = <&dp_calibration>;
+			nvmem-cell-names = "dp_calibration_data";
+			power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+			max-linkrate-mhz = <8100>;
+			status = "disabled";
+		};
+
+		dp_tx: dp-tx@1c600000 {
+			compatible = "mediatek,mt8195-dp-tx";
+			reg = <0 0x1c600000 0 0x8000>;
+			nvmem-cells = <&dp_calibration>;
+			nvmem-cell-names = "dp_calibration_data";
+			power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+			max-linkrate-mhz = <8100>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.18.0

[PATCH v4 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports

[Bo-Chen Chen]

Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 ports.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..303dc32c64dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,24 @@
 	};
 };
 
+&dp_intf0 {
+	status = "okay";
+
+	port {
+		dp_intf0_out: endpoint {
+		};
+	};
+};
+
+&dp_intf1 {
+	status = "okay";
+
+	port {
+		dp_intf1_out: endpoint {
+		};
+	};
+};
+
 &i2c0 {
 	status = "okay";
 
-- 
2.18.0

[PATCH v4 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support

[Bo-Chen Chen]

In cherry projects, we use edptx as the internal display interface
and use dptx as the external display interface. To support this, we
need to add more properties.

- Add pinctrls for edptx and dptx.
- Add ports for edptx and dptx.

The port connections for the internal and external display:
dp-intf0 -> edptx -> panel
dp-intf1 -> dptx

The edptx endpoint is kept empty for now, as the panel addition will
come in a later commit.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 303dc32c64dc..560103e29017 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -125,6 +125,7 @@
 
 	port {
 		dp_intf0_out: endpoint {
+			remote-endpoint = <&edp_in>;
 		};
 	};
 };
@@ -134,6 +135,59 @@
 
 	port {
 		dp_intf1_out: endpoint {
+			remote-endpoint = <&dptx_in>;
+		};
+	};
+};
+
+&edp_tx {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&edptx_pins_default>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			edp_in: endpoint {
+				remote-endpoint = <&dp_intf0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			edp_out: endpoint {
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&dp_tx {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&dptx_pin>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dptx_in: endpoint {
+				remote-endpoint = <&dp_intf1_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dptx_out: endpoint {
+				data-lanes = <0 1 2 3>;
+			};
 		};
 	};
 };
@@ -497,6 +551,20 @@
 		};
 	};
 
+	edptx_pins_default: edptx-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
+			bias-pull-up;
+		};
+	};
+
+	dptx_pin: dptx-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
+			bias-pull-up;
+		};
+	};
+
 	i2c0_pins: i2c0-default-pins {
 		pins-bus {
 			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
-- 
2.18.0

Re: [PATCH v4 2/4] arm64: dts: mt8195: Add edptx and dptx nodes

[Matthias Brugger]

On 10/11/2022 07:37, Bo-Chen Chen wrote:
> In MT8195, we use edptx as the internal display interface and use
> dptx as the external display interface. Therefore, we need to add
> these nodes to support the internal display and the external display.
> 
> - Add dp calibration data in the efuse node.
> - Add edptx and dptx nodes for MT8195.
> 
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index c380738d10cb..7acbef5a4517 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1244,6 +1244,9 @@
>   				reg = <0x189 0x2>;
>   				bits = <7 5>;
>   			};
> +			dp_calibration: dp-data@1ac {
> +				reg = <0x1ac 0x10>;
> +			};
>   		};
>   
>   		u3phy2: t-phy@11c40000 {
> @@ -2205,5 +2208,27 @@
>   			clock-names = "engine", "pixel", "pll";
>   			status = "disabled";
>   		};
> +
> +		edp_tx: edp-tx@1c500000 {
> +			compatible = "mediatek,mt8195-edp-tx";
> +			reg = <0 0x1c500000 0 0x8000>;
> +			nvmem-cells = <&dp_calibration>;
> +			nvmem-cell-names = "dp_calibration_data";
> +			power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
> +			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
> +			max-linkrate-mhz = <8100>;
> +			status = "disabled";
> +		};
> +
> +		dp_tx: dp-tx@1c600000 {
> +			compatible = "mediatek,mt8195-dp-tx";
> +			reg = <0 0x1c600000 0 0x8000>;
> +			nvmem-cells = <&dp_calibration>;
> +			nvmem-cell-names = "dp_calibration_data";
> +			power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
> +			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
> +			max-linkrate-mhz = <8100>;
> +			status = "disabled";
> +		};

For some not really obvious reasons we get the following errors with
make CHECK_DTBS=1 mediatek/mt8195-cherry-tomato-r2.dtb

arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0: 
/soc/edp-tx@1c500000: failed to match any schema with compatible: 
['mediatek,mt8195-edp-tx']
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0: 
/soc/dp-tx@1c600000: failed to match any schema with compatible: 
['mediatek,mt8195-dp-tx']

Can you please see how to fix this. Tested with next-20221111.

Regards,
Matthias

>   	};
>   };

Re: [PATCH v4 2/4] arm64: dts: mt8195: Add edptx and dptx nodes

[Rex-BC Chen (陳柏辰)]

On Fri, 2022-11-11 at 13:22 +0100, Matthias Brugger wrote:
> 
> On 10/11/2022 07:37, Bo-Chen Chen wrote:
> > In MT8195, we use edptx as the internal display interface and use
> > dptx as the external display interface. Therefore, we need to add
> > these nodes to support the internal display and the external
> > display.
> > 
> > - Add dp calibration data in the efuse node.
> > - Add edptx and dptx nodes for MT8195.
> > 
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25
> > ++++++++++++++++++++++++
> >   1 file changed, 25 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index c380738d10cb..7acbef5a4517 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1244,6 +1244,9 @@
> >   				reg = <0x189 0x2>;
> >   				bits = <7 5>;
> >   			};
> > +			dp_calibration: dp-data@1ac {
> > +				reg = <0x1ac 0x10>;
> > +			};
> >   		};
> >   
> >   		u3phy2: t-phy@11c40000 {
> > @@ -2205,5 +2208,27 @@
> >   			clock-names = "engine", "pixel", "pll";
> >   			status = "disabled";
> >   		};
> > +
> > +		edp_tx: edp-tx@1c500000 {
> > +			compatible = "mediatek,mt8195-edp-tx";
> > +			reg = <0 0x1c500000 0 0x8000>;
> > +			nvmem-cells = <&dp_calibration>;
> > +			nvmem-cell-names = "dp_calibration_data";
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_EPD_TX>;
> > +			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			max-linkrate-mhz = <8100>;
> > +			status = "disabled";
> > +		};
> > +
> > +		dp_tx: dp-tx@1c600000 {
> > +			compatible = "mediatek,mt8195-dp-tx";
> > +			reg = <0 0x1c600000 0 0x8000>;
> > +			nvmem-cells = <&dp_calibration>;
> > +			nvmem-cell-names = "dp_calibration_data";
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_DP_TX>;
> > +			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			max-linkrate-mhz = <8100>;
> > +			status = "disabled";
> > +		};
> 
> For some not really obvious reasons we get the following errors with
> make CHECK_DTBS=1 mediatek/mt8195-cherry-tomato-r2.dtb
> 
> arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0: 
> /soc/edp-tx@1c500000: failed to match any schema with compatible: 
> ['mediatek,mt8195-edp-tx']
> arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0: 
> /soc/dp-tx@1c600000: failed to match any schema with compatible: 
> ['mediatek,mt8195-dp-tx']
> 
> Can you please see how to fix this. Tested with next-20221111.
> 
> Regards,
> Matthias
> 

Hello Matthias,

I can not reproduce this issue in my local environment, but I am sure
the binding is in kernel master branch (v6.1-rc5):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml?h=v6.1-rc5

It's strange that the message you provided said it can not find any
schema with ['mediatek,mt8195-edp-tx'] and ['mediatek,mt8195-dp-tx'].

BRs,
Bo-Chen

> >   	};
> >   };

Re: [PATCH v4 2/4] arm64: dts: mt8195: Add edptx and dptx nodes

[AngeloGioacchino Del Regno]

Il 15/11/22 08:58, Rex-BC Chen (陳柏辰) ha scritto:
> On Fri, 2022-11-11 at 13:22 +0100, Matthias Brugger wrote:
>>
>> On 10/11/2022 07:37, Bo-Chen Chen wrote:
>>> In MT8195, we use edptx as the internal display interface and use
>>> dptx as the external display interface. Therefore, we need to add
>>> these nodes to support the internal display and the external
>>> display.
>>>
>>> - Add dp calibration data in the efuse node.
>>> - Add edptx and dptx nodes for MT8195.
>>>
>>> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25
>>> ++++++++++++++++++++++++
>>>    1 file changed, 25 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
>>> index c380738d10cb..7acbef5a4517 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
>>> @@ -1244,6 +1244,9 @@
>>>    				reg = <0x189 0x2>;
>>>    				bits = <7 5>;
>>>    			};
>>> +			dp_calibration: dp-data@1ac {
>>> +				reg = <0x1ac 0x10>;
>>> +			};
>>>    		};
>>>    
>>>    		u3phy2: t-phy@11c40000 {
>>> @@ -2205,5 +2208,27 @@
>>>    			clock-names = "engine", "pixel", "pll";
>>>    			status = "disabled";
>>>    		};
>>> +
>>> +		edp_tx: edp-tx@1c500000 {
>>> +			compatible = "mediatek,mt8195-edp-tx";
>>> +			reg = <0 0x1c500000 0 0x8000>;
>>> +			nvmem-cells = <&dp_calibration>;
>>> +			nvmem-cell-names = "dp_calibration_data";
>>> +			power-domains = <&spm
>>> MT8195_POWER_DOMAIN_EPD_TX>;
>>> +			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			max-linkrate-mhz = <8100>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		dp_tx: dp-tx@1c600000 {
>>> +			compatible = "mediatek,mt8195-dp-tx";
>>> +			reg = <0 0x1c600000 0 0x8000>;
>>> +			nvmem-cells = <&dp_calibration>;
>>> +			nvmem-cell-names = "dp_calibration_data";
>>> +			power-domains = <&spm
>>> MT8195_POWER_DOMAIN_DP_TX>;
>>> +			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			max-linkrate-mhz = <8100>;
>>> +			status = "disabled";
>>> +		};
>>
>> For some not really obvious reasons we get the following errors with
>> make CHECK_DTBS=1 mediatek/mt8195-cherry-tomato-r2.dtb
>>
>> arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0:
>> /soc/edp-tx@1c500000: failed to match any schema with compatible:
>> ['mediatek,mt8195-edp-tx']
>> arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dtb:0:0:
>> /soc/dp-tx@1c600000: failed to match any schema with compatible:
>> ['mediatek,mt8195-dp-tx']
>>
>> Can you please see how to fix this. Tested with next-20221111.
>>
>> Regards,
>> Matthias
>>
> 
> Hello Matthias,
> 
> I can not reproduce this issue in my local environment, but I am sure
> the binding is in kernel master branch (v6.1-rc5):
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml?h=v6.1-rc5
> 
> It's strange that the message you provided said it can not find any
> schema with ['mediatek,mt8195-edp-tx'] and ['mediatek,mt8195-dp-tx'].
> 

Matthias, I can't reproduce that either... perhaps there's something odd that's
going on with your environment?

Cheers

Re: [PATCH v4 0/4] Add dp-intf and dp nodes

[Matthias Brugger]

On 10/11/2022 07:37, Bo-Chen Chen wrote:
> This series add MediaTek dp-intf nodes and dp nodes.
> This series is based on linux-next-20220915.
> 
> Changes for v4:
> 1. Rebase to linux-next 20221109.
> 
> Changes for v3:
> 1. Update commit message for "arm64: dts: mediatek: cherry: Add edptx and dptx support".
> 
> Changes for v2:
> 1. Update commit messages.
> 2. reorder the place of "status = "disabled";"
> 3. reorder the place of dp-intf.
> 
> Bo-Chen Chen (4):
>    arm64: dts: mt8195: Add dp-intf nodes
>    arm64: dts: mt8195: Add edptx and dptx nodes
>    arm64: dts: mediatek: cherry: Add dp-intf ports
>    arm64: dts: mediatek: cherry: Add edptx and dptx support
> 

Whole series applied, thanks!

>   .../boot/dts/mediatek/mt8195-cherry.dtsi      | 86 +++++++++++++++++++
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 48 +++++++++++
>   2 files changed, 134 insertions(+)
>