[PATCH] spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation

[PATCH] spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation

[Nathan Barrett-Morrison]

This Cadence QSPI IP has a 4-bit clock divisor field
for baud rate division.  For example:

0b0000 = /2
0b0001 = /4
0b0010 = /6
...
0b1111 = /32

The maximum divisor is 32
(when div = CQSPI_REG_CONFIG_BAUD_MASK).

If we assume a reference clock of 500MHz and we set
our spi-max-frequency to something low, such as 10 MHz.
The calculated bit field for the divisor ends up being:

DIV_ROUND_UP(500000000/(2*10000000))-1 = 25

25 is 0b11001... which truncates to a divisor field of 0b1001 (or /20).

This is higher than our anticipated max-frequency of 10MHz
(500MHz/20 = 25 MHz).  Instead, let's make sure we're always using
the maximum divisor (/32) in this case and give the user a warning about
the rate adjustment.

Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
---
 drivers/spi/spi-cadence-quadspi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 447230547945..21b60b354404 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1119,6 +1119,14 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 	/* Recalculate the baudrate divisor based on QSPI specification. */
 	div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 
+	/* Maximum baud divisor */
+	if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
+		div = CQSPI_REG_CONFIG_BAUD_MASK;
+		dev_warn(&cqspi->pdev->dev,
+			"Unable to adjust clock <= %d hz. Reduced to %d hz\n",
+			cqspi->sclk, ref_clk_hz/((div+1)*2));
+	}
+
 	reg = readl(reg_base + CQSPI_REG_CONFIG);
 	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 	reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
-- 
2.30.2

Re: [PATCH] spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation

[Mark Brown]

On Mon, 28 Nov 2022 11:41:47 -0500, Nathan Barrett-Morrison wrote:
> This Cadence QSPI IP has a 4-bit clock divisor field
> for baud rate division.  For example:
> 
> 0b0000 = /2
> 0b0001 = /4
> 0b0010 = /6
> ...
> 0b1111 = /32
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation
      commit: f8fc65e50ad71c139a12a96e64eeba5005e491d5

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark