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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
	tony.luck@intel.com
Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	james.morse@arm.com, mchehab@kernel.org, rric@kernel.org,
	linux-edac@vger.kernel.org, quic_ppareek@quicinc.com,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	stable@vger.kernel.org
Subject: [PATCH 10/12] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks
Date: Wed,  7 Dec 2022 19:29:19 +0530	[thread overview]
Message-ID: <20221207135922.314827-11-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20221207135922.314827-1-manivannan.sadhasivam@linaro.org>

The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Cc: <stable@vger.kernel.org> # 5.18
Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 570475040d95..12549a2912c6 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 {
 
 		system-cache-controller@19200000 {
 			compatible = "qcom,sm8450-llcc";
-			reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
-			reg-names = "llcc_base", "llcc_broadcast_base";
+			reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
+			      <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
+			      <0 0x19a00000 0 0x80000>;
+			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+				    "llcc3_base", "llcc_broadcast_base";
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-- 
2.25.1


  parent reply	other threads:[~2022-12-07 14:02 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-07 13:59 [PATCH 00/12] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 01/12] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2022-12-08  3:15   ` Sai Prakash Ranjan
2022-12-12  5:54     ` Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 02/12] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2022-12-07 16:08   ` Bjorn Andersson
2022-12-07 16:53     ` Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 03/12] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 04/12] arm64: dts: qcom: sc7180: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 05/12] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 06/12] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 07/12] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 08/12] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 09/12] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2022-12-07 13:59 ` Manivannan Sadhasivam [this message]
2022-12-07 13:59 ` [PATCH 11/12] arm64: dts: qcom: sm6350: " Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 12/12] llcc/edac: Fix the base address used for accessing " Manivannan Sadhasivam
2022-12-07 14:06   ` Manivannan Sadhasivam
2022-12-07 13:59 ` [PATCH 12/12] qcom: " Manivannan Sadhasivam
2022-12-07 16:17   ` Bjorn Andersson
2022-12-08  9:16 ` [PATCH 00/12] Qcom: LLCC/EDAC: Fix base address used for " Luca Weiss
2022-12-12  8:31   ` Manivannan Sadhasivam

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