From: Yanhong Wang <yanhong.wang@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <netdev@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: "David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Richard Cochran <richardcochran@gmail.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Peter Geis <pgwipeout@gmail.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>
Subject: [PATCH v2 9/9] riscv: dts: starfive: visionfive-v2: Add phy clock delay train configuration
Date: Fri, 16 Dec 2022 15:06:32 +0800 [thread overview]
Message-ID: <20221216070632.11444-10-yanhong.wang@starfivetech.com> (raw)
In-Reply-To: <20221216070632.11444-1-yanhong.wang@starfivetech.com>
In view of the particularity of StarFive JH7110 SoC, the PHY clock delay
train configuration parameters must be adjusted for StarFive VisionFive
v2 board.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
.../jh7110-starfive-visionfive-v2.dts | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
index c8946cf3a268..81329d67ef0f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
@@ -15,6 +15,8 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
@@ -114,3 +116,29 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&gmac0 {
+ status = "okay";
+};
+
+&phy0 {
+ rxc_dly_en = <1>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0xa>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x1>;
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&phy1 {
+ rxc_dly_en = <0>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x0>;
+};
--
2.17.1
prev parent reply other threads:[~2022-12-16 7:06 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-16 7:06 [PATCH v2 0/9] Add Ethernet driver for StarFive JH7110 SoC Yanhong Wang
2022-12-16 7:06 ` [PATCH v2 1/9] dt-bindings: net: snps,dwmac: Add dwmac-5.20 version Yanhong Wang
2022-12-16 7:06 ` [PATCH v2 2/9] dt-bindings: net: snps,dwmac: Update the maxitems number of resets and reset-names Yanhong Wang
2022-12-16 11:03 ` Krzysztof Kozlowski
2022-12-20 6:48 ` yanhong wang
2022-12-20 9:21 ` Krzysztof Kozlowski
2022-12-27 7:48 ` yanhong wang
2022-12-27 8:18 ` Krzysztof Kozlowski
2022-12-16 7:06 ` [PATCH v2 3/9] net: stmmac: platform: Add snps,dwmac-5.20 IP compatible string Yanhong Wang
2022-12-16 7:06 ` [PATCH v2 4/9] dt-bindings: net: Add bindings for StarFive dwmac Yanhong Wang
2022-12-16 11:05 ` Krzysztof Kozlowski
2022-12-20 6:53 ` yanhong wang
2022-12-16 11:06 ` Krzysztof Kozlowski
2022-12-20 6:57 ` yanhong wang
2022-12-20 18:03 ` Rob Herring
2022-12-16 7:06 ` [PATCH v2 5/9] dt-bindings: net: motorcomm: add support for Motorcomm YT8531 Yanhong Wang
2022-12-16 11:15 ` Krzysztof Kozlowski
2022-12-27 9:38 ` yanhong wang
2022-12-27 9:52 ` Krzysztof Kozlowski
2022-12-28 3:23 ` yanhong wang
2022-12-28 9:11 ` Krzysztof Kozlowski
2022-12-28 9:24 ` yanhong wang
2022-12-16 7:06 ` [PATCH v2 6/9] net: phy: motorcomm: Add YT8531 phy support Yanhong Wang
2022-12-16 8:41 ` Arun.Ramadoss
2022-12-16 11:58 ` Heiner Kallweit
2022-12-21 1:16 ` yanhong wang
2022-12-20 14:20 ` Andrew Lunn
2022-12-16 7:06 ` [PATCH v2 7/9] net: stmmac: Add glue layer for StarFive JH71x0 SoCs Yanhong Wang
2022-12-16 11:19 ` Krzysztof Kozlowski
2022-12-16 7:06 ` [PATCH v2 8/9] riscv: dts: starfive: jh7110: Add ethernet device node Yanhong Wang
2022-12-16 7:06 ` Yanhong Wang [this message]
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