* [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC
@ 2023-01-02 22:18 Prabhakar
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series does the following:
* Adds IRQC support to the RZ/G2UL SoC.
* Drops mapping NMI interrupt as part of IRQ domain
* Parses interrupts based in interrupt-names
* Includes a fix for pinctrl driver when using GPIO pins as interrupts
* Adds PHY interrupt support for ETH{0/1}
v2->v3
* Dropped skipping of NMI interrupt, as it can be used as an external
interrupt.
* Dropped parsing interrupts based on names
* Dropped "renesas,rzg2ul-irqc" compatible string
v1->v2
* Updated binding doc
* Dropped mapping NMI interrupt as part of IRQ domain
* Fixed review comments pointed by Geert
* Added support to parse interrupts by name
* Added compile time checks for gpio config arrays
RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (6):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document
RZ/G2UL SoC
pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts
pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
arm64: dts: renesas: r9a07g043u: Add IRQC node
arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO
interrupts
arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for
ETH{0/1}
.../renesas,rzg2l-irqc.yaml | 225 +++++++++++++-----
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 +
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++++
.../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +-
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +-
5 files changed, 270 insertions(+), 65 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-08 20:52 ` Rob Herring
` (2 more replies)
2023-01-02 22:18 ` [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Prabhakar
` (6 subsequent siblings)
7 siblings, 3 replies; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
is almost identical to one found on the RZ/G2L SoC the only difference
being it can support BUS_ERR_INT for which it has additional registers.
Hence new generic compatible string "renesas,r9a07g043u-irqc" is added
for RZ/G2UL SoC.
Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
interrupt-names property is added so that we can parse them based on
names.
While at it updated the example node to four spaces and added
interrupt-names property.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
* Dropped RZ/G2UL specific string
v1- > v2
* Dropped RB tags
* Added generic compatible string for rzg2ul
* Added interrupt-names
* Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
* Updated example node with interrupt-names
* Used 4 spaces for example node
---
.../renesas,rzg2l-irqc.yaml | 225 +++++++++++++-----
1 file changed, 170 insertions(+), 55 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 33b90e975e33..fc900ce2fe0a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -19,13 +19,11 @@ description: |
- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
stand-up edge detection interrupts)
-allOf:
- - $ref: /schemas/interrupt-controller.yaml#
-
properties:
compatible:
items:
- enum:
+ - renesas,r9a07g043u-irqc # RZ/G2UL
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
- const: renesas,rzg2l-irqc
@@ -44,7 +42,96 @@ properties:
maxItems: 1
interrupts:
- maxItems: 41
+ minItems: 41
+ items:
+ - description: NMI interrupt
+ - description: IRQ0 interrupt
+ - description: IRQ1 interrupt
+ - description: IRQ2 interrupt
+ - description: IRQ3 interrupt
+ - description: IRQ4 interrupt
+ - description: IRQ5 interrupt
+ - description: IRQ6 interrupt
+ - description: IRQ7 interrupt
+ - description: GPIO interrupt, TINT0
+ - description: GPIO interrupt, TINT1
+ - description: GPIO interrupt, TINT2
+ - description: GPIO interrupt, TINT3
+ - description: GPIO interrupt, TINT4
+ - description: GPIO interrupt, TINT5
+ - description: GPIO interrupt, TINT6
+ - description: GPIO interrupt, TINT7
+ - description: GPIO interrupt, TINT8
+ - description: GPIO interrupt, TINT9
+ - description: GPIO interrupt, TINT10
+ - description: GPIO interrupt, TINT11
+ - description: GPIO interrupt, TINT12
+ - description: GPIO interrupt, TINT13
+ - description: GPIO interrupt, TINT14
+ - description: GPIO interrupt, TINT15
+ - description: GPIO interrupt, TINT16
+ - description: GPIO interrupt, TINT17
+ - description: GPIO interrupt, TINT18
+ - description: GPIO interrupt, TINT19
+ - description: GPIO interrupt, TINT20
+ - description: GPIO interrupt, TINT21
+ - description: GPIO interrupt, TINT22
+ - description: GPIO interrupt, TINT23
+ - description: GPIO interrupt, TINT24
+ - description: GPIO interrupt, TINT25
+ - description: GPIO interrupt, TINT26
+ - description: GPIO interrupt, TINT27
+ - description: GPIO interrupt, TINT28
+ - description: GPIO interrupt, TINT29
+ - description: GPIO interrupt, TINT30
+ - description: GPIO interrupt, TINT31
+ - description: Bus error interrupt
+
+ interrupt-names:
+ minItems: 41
+ items:
+ - const: nmi
+ - const: irq0
+ - const: irq1
+ - const: irq2
+ - const: irq3
+ - const: irq4
+ - const: irq5
+ - const: irq6
+ - const: irq7
+ - const: tint0
+ - const: tint1
+ - const: tint2
+ - const: tint3
+ - const: tint4
+ - const: tint5
+ - const: tint6
+ - const: tint7
+ - const: tint8
+ - const: tint9
+ - const: tint10
+ - const: tint11
+ - const: tint12
+ - const: tint13
+ - const: tint14
+ - const: tint15
+ - const: tint16
+ - const: tint17
+ - const: tint18
+ - const: tint19
+ - const: tint20
+ - const: tint21
+ - const: tint22
+ - const: tint23
+ - const: tint24
+ - const: tint25
+ - const: tint26
+ - const: tint27
+ - const: tint28
+ - const: tint29
+ - const: tint30
+ - const: tint31
+ - const: bus-err
clocks:
maxItems: 2
@@ -72,6 +159,23 @@ required:
- power-domains
- resets
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g043u-irqc
+ then:
+ properties:
+ interrupts:
+ minItems: 42
+ interrupt-names:
+ minItems: 42
+ required:
+ - interrupt-names
+
unevaluatedProperties: false
examples:
@@ -80,55 +184,66 @@ examples:
#include <dt-bindings/clock/r9a07g044-cpg.h>
irqc: interrupt-controller@110a0000 {
- compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
- reg = <0x110a0000 0x10000>;
- #interrupt-cells = <2>;
- #address-cells = <0>;
- interrupt-controller;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
- <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
- clock-names = "clk", "pclk";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_IA55_RESETN>;
+ compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
+ reg = <0x110a0000 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31";
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-25 11:32 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Prabhakar
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also
the pin configs are completely different. This patch makes sure we use the
appropriate pin configs for each SoC (which is passed as part of the OF
data) while configuring the GPIO pin as interrupts instead of using
rzg2l_gpio_configs[] for all the SoCs.
Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2 -> v3
* No change
v1 -> v2
* Fixed comments pointed by Geert for variable naming
* Added RB tag
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 5aa3836dbc22..6f762097557a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -130,6 +130,7 @@ struct rzg2l_dedicated_configs {
struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u32 *port_pin_configs;
+ unsigned int n_ports;
struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
@@ -1124,7 +1125,7 @@ static struct {
}
};
-static int rzg2l_gpio_get_gpioint(unsigned int virq)
+static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{
unsigned int gpioint;
unsigned int i;
@@ -1133,13 +1134,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq)
port = virq / 8;
bit = virq % 8;
- if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
- bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
+ if (port >= data->n_ports ||
+ bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
return -EINVAL;
gpioint = bit;
for (i = 0; i < port; i++)
- gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
+ gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
return gpioint;
}
@@ -1239,7 +1240,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned long flags;
int gpioint, irq;
- gpioint = rzg2l_gpio_get_gpioint(child);
+ gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
if (gpioint < 0)
return gpioint;
@@ -1313,8 +1314,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
port = offset / 8;
bit = offset % 8;
- if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
- bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
+ if (port >= pctrl->data->n_ports ||
+ bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
clear_bit(offset, valid_mask);
}
}
@@ -1519,6 +1520,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
@@ -1527,6 +1529,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs,
+ .n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
2023-01-02 22:18 ` [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-25 11:32 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node Prabhakar
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each
supported SoC.
While at it, for readability set n_port_pins based on the GPIO pin configs
and not on GPIO names for r9a07g044_data as done for r9a07g043_data.
Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2 -> v3
* No change
v1 -> v2
* New patch
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 6f762097557a..04b31f0c6b34 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1468,6 +1468,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
struct rzg2l_pinctrl *pctrl;
int ret;
+ BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
+ BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@@ -1531,7 +1537,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pin_configs = rzg2l_gpio_configs,
.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
- .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
+ .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
` (2 preceding siblings ...)
2023-01-02 22:18 ` [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-25 11:35 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts Prabhakar
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2 -> v3
* Used "renesas,rzg2l-irqc" instead of "renesas,rzg2ul-irqc"
v1 -> v2
* Moved irqc node completely to rzg2ul SoC DTSI
* Added interrupt-names
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 68 +++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 6af5f3bca2d1..4ebf7335cdb9 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -52,6 +52,74 @@ timer {
&soc {
interrupt-parent = <&gic>;
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g043u-irqc",
+ "renesas,rzg2l-irqc";
+ reg = <0 0x110a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_IA55_RESETN>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
` (3 preceding siblings ...)
2023-01-02 22:18 ` [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-25 11:36 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Prabhakar
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add required properties in pinctrl node to handle GPIO interrupts.
Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
continues without waiting for IRQC to probe.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2 -> v3
* No change
v1 -> v2
* No change
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 3f7d451b1199..c8a83e42c4f3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 152>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_GPIO_RSTN>,
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 4ebf7335cdb9..9d854706ada5 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -49,6 +49,10 @@ timer {
};
};
+&pinctrl {
+ interrupt-parent = <&irqc>;
+};
+
&soc {
interrupt-parent = <&gic>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
` (4 preceding siblings ...)
2023-01-02 22:18 ` [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts Prabhakar
@ 2023-01-02 22:18 ` Prabhakar
2023-01-25 13:03 ` Geert Uytterhoeven
2023-01-09 13:14 ` [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Linus Walleij
2023-01-22 18:32 ` Lad, Prabhakar
7 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2023-01-02 22:18 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij
Cc: linux-kernel, devicetree, linux-renesas-soc, linux-gpio,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2 -> v3
* No change
v1 -> v2
* No change
---
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 931efc07d6fb..49ecd33aeeb8 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -104,6 +107,8 @@ phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -151,7 +156,8 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
- <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
};
eth1_pins: eth1 {
@@ -169,7 +175,8 @@ eth1_pins: eth1 {
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
- <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
};
sdhi0_emmc_pins: sd0emmc {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
@ 2023-01-08 20:52 ` Rob Herring
2023-01-25 11:25 ` Geert Uytterhoeven
2023-10-04 13:35 ` Lad, Prabhakar
2 siblings, 0 replies; 17+ messages in thread
From: Rob Herring @ 2023-01-08 20:52 UTC (permalink / raw)
To: Prabhakar
Cc: Geert Uytterhoeven, Magnus Damm, devicetree, Biju Das,
linux-renesas-soc, linux-gpio, Marc Zyngier, linux-kernel,
Lad Prabhakar, Thomas Gleixner, Krzysztof Kozlowski,
Linus Walleij, Rob Herring
On Mon, 02 Jan 2023 22:18:10 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> is almost identical to one found on the RZ/G2L SoC the only difference
> being it can support BUS_ERR_INT for which it has additional registers.
> Hence new generic compatible string "renesas,r9a07g043u-irqc" is added
> for RZ/G2UL SoC.
>
> Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> interrupt-names property is added so that we can parse them based on
> names.
>
> While at it updated the example node to four spaces and added
> interrupt-names property.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Dropped RZ/G2UL specific string
>
> v1- > v2
> * Dropped RB tags
> * Added generic compatible string for rzg2ul
> * Added interrupt-names
> * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> * Updated example node with interrupt-names
> * Used 4 spaces for example node
> ---
> .../renesas,rzg2l-irqc.yaml | 225 +++++++++++++-----
> 1 file changed, 170 insertions(+), 55 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
` (5 preceding siblings ...)
2023-01-02 22:18 ` [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Prabhakar
@ 2023-01-09 13:14 ` Linus Walleij
2023-01-22 18:32 ` Lad, Prabhakar
7 siblings, 0 replies; 17+ messages in thread
From: Linus Walleij @ 2023-01-09 13:14 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, linux-kernel, devicetree,
linux-renesas-soc, linux-gpio, Biju Das, Lad Prabhakar
On Mon, Jan 2, 2023 at 11:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> This patch series does the following:
> * Adds IRQC support to the RZ/G2UL SoC.
> * Drops mapping NMI interrupt as part of IRQ domain
> * Parses interrupts based in interrupt-names
> * Includes a fix for pinctrl driver when using GPIO pins as interrupts
> * Adds PHY interrupt support for ETH{0/1}
The pinctrl portions look OK to me FWIW
Acked-by: Linus Walleij <linus.walleij@linaro.org>
If any of this is to be merged into the pinctrl tree I expect to get it as
pull request from Geert who maintains the Renesas pinctrl tree,
else tell me what to do!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
` (6 preceding siblings ...)
2023-01-09 13:14 ` [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Linus Walleij
@ 2023-01-22 18:32 ` Lad, Prabhakar
7 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2023-01-22 18:32 UTC (permalink / raw)
To: Geert Uytterhoeven, Geert Uytterhoeven
Cc: Thomas Gleixner, Linus Walleij, Magnus Damm, Krzysztof Kozlowski,
Rob Herring, Marc Zyngier, linux-kernel, devicetree,
linux-renesas-soc, linux-gpio, Biju Das, Lad Prabhakar
Hi Geert,
On Mon, Jan 2, 2023 at 10:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> This patch series does the following:
> * Adds IRQC support to the RZ/G2UL SoC.
> * Drops mapping NMI interrupt as part of IRQ domain
> * Parses interrupts based in interrupt-names
> * Includes a fix for pinctrl driver when using GPIO pins as interrupts
> * Adds PHY interrupt support for ETH{0/1}
>
> v2->v3
> * Dropped skipping of NMI interrupt, as it can be used as an external
> interrupt.
> * Dropped parsing interrupts based on names
> * Dropped "renesas,rzg2ul-irqc" compatible string
>
> v1->v2
> * Updated binding doc
> * Dropped mapping NMI interrupt as part of IRQ domain
> * Fixed review comments pointed by Geert
> * Added support to parse interrupts by name
> * Added compile time checks for gpio config arrays
>
> RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (6):
> dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document
> RZ/G2UL SoC
> pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts
> pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
> arm64: dts: renesas: r9a07g043u: Add IRQC node
> arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO
> interrupts
> arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for
> ETH{0/1}
>
Gentle ping.
Cheers,
Prabhakar
> .../renesas,rzg2l-irqc.yaml | 225 +++++++++++++-----
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 +
> arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++++
> .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +-
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +-
> 5 files changed, 270 insertions(+), 65 deletions(-)
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
2023-01-08 20:52 ` Rob Herring
@ 2023-01-25 11:25 ` Geert Uytterhoeven
2023-10-04 13:35 ` Lad, Prabhakar
2 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 11:25 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Magnus Damm, Linus Walleij, linux-kernel, devicetree,
linux-renesas-soc, linux-gpio, Biju Das, Lad Prabhakar
On Mon, Jan 2, 2023 at 11:19 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> is almost identical to one found on the RZ/G2L SoC the only difference
> being it can support BUS_ERR_INT for which it has additional registers.
> Hence new generic compatible string "renesas,r9a07g043u-irqc" is added
> for RZ/G2UL SoC.
>
> Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> interrupt-names property is added so that we can parse them based on
> names.
>
> While at it updated the example node to four spaces and added
> interrupt-names property.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Dropped RZ/G2UL specific string
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts
2023-01-02 22:18 ` [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Prabhakar
@ 2023-01-25 11:32 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 11:32 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij, linux-kernel,
devicetree, linux-renesas-soc, linux-gpio, Biju Das,
Lad Prabhakar
On Mon, Jan 2, 2023 at 11:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also
> the pin configs are completely different. This patch makes sure we use the
> appropriate pin configs for each SoC (which is passed as part of the OF
> data) while configuring the GPIO pin as interrupts instead of using
> rzg2l_gpio_configs[] for all the SoCs.
>
> Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2 -> v3
> * No change
Thanks, will queue in renesas-pinctrl-for-v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
2023-01-02 22:18 ` [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Prabhakar
@ 2023-01-25 11:32 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 11:32 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij, linux-kernel,
devicetree, linux-renesas-soc, linux-gpio, Biju Das,
Lad Prabhakar
On Mon, Jan 2, 2023 at 11:19 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each
> supported SoC.
>
> While at it, for readability set n_port_pins based on the GPIO pin configs
> and not on GPIO names for r9a07g044_data as done for r9a07g043_data.
>
> Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2 -> v3
> * No change
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node
2023-01-02 22:18 ` [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node Prabhakar
@ 2023-01-25 11:35 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 11:35 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Magnus Damm, Linus Walleij, linux-kernel, devicetree,
linux-renesas-soc, linux-gpio, Biju Das, Lad Prabhakar
On Mon, Jan 2, 2023 at 11:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2 -> v3
> * Used "renesas,rzg2l-irqc" instead of "renesas,rzg2ul-irqc"
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts
2023-01-02 22:18 ` [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts Prabhakar
@ 2023-01-25 11:36 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 11:36 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven, Magnus Damm, Linus Walleij, linux-kernel,
devicetree, linux-renesas-soc, linux-gpio, Biju Das,
Lad Prabhakar
On Mon, Jan 2, 2023 at 11:19 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add required properties in pinctrl node to handle GPIO interrupts.
>
> Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
> is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
> continues without waiting for IRQC to probe.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2 -> v3
> * No change
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
2023-01-02 22:18 ` [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Prabhakar
@ 2023-01-25 13:03 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2023-01-25 13:03 UTC (permalink / raw)
To: Prabhakar
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Magnus Damm, Linus Walleij, linux-kernel, devicetree,
linux-renesas-soc, linux-gpio, Biju Das, Lad Prabhakar
On Mon, Jan 2, 2023 at 11:19 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2 -> v3
> * No change
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
2023-01-08 20:52 ` Rob Herring
2023-01-25 11:25 ` Geert Uytterhoeven
@ 2023-10-04 13:35 ` Lad, Prabhakar
2 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2023-10-04 13:35 UTC (permalink / raw)
To: Marc Zyngier
Cc: Linus Walleij, Magnus Damm, Geert Uytterhoeven,
Krzysztof Kozlowski, Rob Herring, Thomas Gleixner, linux-kernel,
devicetree, linux-renesas-soc, linux-gpio, Biju Das,
Lad Prabhakar
Hi Marc,
On Mon, Jan 2, 2023 at 10:18 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> is almost identical to one found on the RZ/G2L SoC the only difference
> being it can support BUS_ERR_INT for which it has additional registers.
> Hence new generic compatible string "renesas,r9a07g043u-irqc" is added
> for RZ/G2UL SoC.
>
> Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> interrupt-names property is added so that we can parse them based on
> names.
>
> While at it updated the example node to four spaces and added
> interrupt-names property.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Dropped RZ/G2UL specific string
>
> v1- > v2
> * Dropped RB tags
> * Added generic compatible string for rzg2ul
> * Added interrupt-names
> * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> * Updated example node with interrupt-names
> * Used 4 spaces for example node
> ---
> .../renesas,rzg2l-irqc.yaml | 225 +++++++++++++-----
> 1 file changed, 170 insertions(+), 55 deletions(-)
>
Looks like this patch got missed. Could you pick this one up or shall
I just resend this patch.
Cheers,
Prabhakar
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index 33b90e975e33..fc900ce2fe0a 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -19,13 +19,11 @@ description: |
> - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> stand-up edge detection interrupts)
>
> -allOf:
> - - $ref: /schemas/interrupt-controller.yaml#
> -
> properties:
> compatible:
> items:
> - enum:
> + - renesas,r9a07g043u-irqc # RZ/G2UL
> - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> - renesas,r9a07g054-irqc # RZ/V2L
> - const: renesas,rzg2l-irqc
> @@ -44,7 +42,96 @@ properties:
> maxItems: 1
>
> interrupts:
> - maxItems: 41
> + minItems: 41
> + items:
> + - description: NMI interrupt
> + - description: IRQ0 interrupt
> + - description: IRQ1 interrupt
> + - description: IRQ2 interrupt
> + - description: IRQ3 interrupt
> + - description: IRQ4 interrupt
> + - description: IRQ5 interrupt
> + - description: IRQ6 interrupt
> + - description: IRQ7 interrupt
> + - description: GPIO interrupt, TINT0
> + - description: GPIO interrupt, TINT1
> + - description: GPIO interrupt, TINT2
> + - description: GPIO interrupt, TINT3
> + - description: GPIO interrupt, TINT4
> + - description: GPIO interrupt, TINT5
> + - description: GPIO interrupt, TINT6
> + - description: GPIO interrupt, TINT7
> + - description: GPIO interrupt, TINT8
> + - description: GPIO interrupt, TINT9
> + - description: GPIO interrupt, TINT10
> + - description: GPIO interrupt, TINT11
> + - description: GPIO interrupt, TINT12
> + - description: GPIO interrupt, TINT13
> + - description: GPIO interrupt, TINT14
> + - description: GPIO interrupt, TINT15
> + - description: GPIO interrupt, TINT16
> + - description: GPIO interrupt, TINT17
> + - description: GPIO interrupt, TINT18
> + - description: GPIO interrupt, TINT19
> + - description: GPIO interrupt, TINT20
> + - description: GPIO interrupt, TINT21
> + - description: GPIO interrupt, TINT22
> + - description: GPIO interrupt, TINT23
> + - description: GPIO interrupt, TINT24
> + - description: GPIO interrupt, TINT25
> + - description: GPIO interrupt, TINT26
> + - description: GPIO interrupt, TINT27
> + - description: GPIO interrupt, TINT28
> + - description: GPIO interrupt, TINT29
> + - description: GPIO interrupt, TINT30
> + - description: GPIO interrupt, TINT31
> + - description: Bus error interrupt
> +
> + interrupt-names:
> + minItems: 41
> + items:
> + - const: nmi
> + - const: irq0
> + - const: irq1
> + - const: irq2
> + - const: irq3
> + - const: irq4
> + - const: irq5
> + - const: irq6
> + - const: irq7
> + - const: tint0
> + - const: tint1
> + - const: tint2
> + - const: tint3
> + - const: tint4
> + - const: tint5
> + - const: tint6
> + - const: tint7
> + - const: tint8
> + - const: tint9
> + - const: tint10
> + - const: tint11
> + - const: tint12
> + - const: tint13
> + - const: tint14
> + - const: tint15
> + - const: tint16
> + - const: tint17
> + - const: tint18
> + - const: tint19
> + - const: tint20
> + - const: tint21
> + - const: tint22
> + - const: tint23
> + - const: tint24
> + - const: tint25
> + - const: tint26
> + - const: tint27
> + - const: tint28
> + - const: tint29
> + - const: tint30
> + - const: tint31
> + - const: bus-err
>
> clocks:
> maxItems: 2
> @@ -72,6 +159,23 @@ required:
> - power-domains
> - resets
>
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g043u-irqc
> + then:
> + properties:
> + interrupts:
> + minItems: 42
> + interrupt-names:
> + minItems: 42
> + required:
> + - interrupt-names
> +
> unevaluatedProperties: false
>
> examples:
> @@ -80,55 +184,66 @@ examples:
> #include <dt-bindings/clock/r9a07g044-cpg.h>
>
> irqc: interrupt-controller@110a0000 {
> - compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
> - reg = <0x110a0000 0x10000>;
> - #interrupt-cells = <2>;
> - #address-cells = <0>;
> - interrupt-controller;
> - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
> - <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
> - clock-names = "clk", "pclk";
> - power-domains = <&cpg>;
> - resets = <&cpg R9A07G044_IA55_RESETN>;
> + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
> + reg = <0x110a0000 0x10000>;
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "nmi",
> + "irq0", "irq1", "irq2", "irq3",
> + "irq4", "irq5", "irq6", "irq7",
> + "tint0", "tint1", "tint2", "tint3",
> + "tint4", "tint5", "tint6", "tint7",
> + "tint8", "tint9", "tint10", "tint11",
> + "tint12", "tint13", "tint14", "tint15",
> + "tint16", "tint17", "tint18", "tint19",
> + "tint20", "tint21", "tint22", "tint23",
> + "tint24", "tint25", "tint26", "tint27",
> + "tint28", "tint29", "tint30", "tint31";
> + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
> + <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
> + clock-names = "clk", "pclk";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G044_IA55_RESETN>;
> };
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-10-04 13:36 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-02 22:18 [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Prabhakar
2023-01-02 22:18 ` [PATCH v3 1/6] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
2023-01-08 20:52 ` Rob Herring
2023-01-25 11:25 ` Geert Uytterhoeven
2023-10-04 13:35 ` Lad, Prabhakar
2023-01-02 22:18 ` [PATCH v3 2/6] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Prabhakar
2023-01-25 11:32 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 3/6] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Prabhakar
2023-01-25 11:32 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 4/6] arm64: dts: renesas: r9a07g043u: Add IRQC node Prabhakar
2023-01-25 11:35 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 5/6] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts Prabhakar
2023-01-25 11:36 ` Geert Uytterhoeven
2023-01-02 22:18 ` [PATCH v3 6/6] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Prabhakar
2023-01-25 13:03 ` Geert Uytterhoeven
2023-01-09 13:14 ` [PATCH v3 0/6] Add IRQC support to RZ/G2UL SoC Linus Walleij
2023-01-22 18:32 ` Lad, Prabhakar
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