From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Guo Ren <guoren@kernel.org>
Subject: [PATCH v4 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage
Date: Sun, 15 Jan 2023 23:49:53 +0800 [thread overview]
Message-ID: <20230115154953.831-14-jszhang@kernel.org> (raw)
In-Reply-To: <20230115154953.831-1-jszhang@kernel.org>
All users have switched to riscv_has_extension_*, remove unused
definitions, vars and related setting code.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/hwcap.h | 31 -------------------------------
arch/riscv/kernel/cpufeature.c | 9 ---------
2 files changed, 40 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 1767a9ce1a04..e3749bee5c24 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -60,19 +60,6 @@ enum {
extern unsigned long elf_hwcap;
-
-/*
- * This enum represents the logical ID for each RISC-V ISA extension static
- * keys. We can use static key to optimize code path if some ISA extensions
- * are available.
- */
-enum riscv_isa_ext_key {
- RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
- RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
- RISCV_ISA_EXT_KEY_SVINVAL,
- RISCV_ISA_EXT_KEY_MAX,
-};
-
struct riscv_isa_ext_data {
/* Name of the extension displayed to userspace via /proc/cpuinfo */
char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
@@ -80,24 +67,6 @@ struct riscv_isa_ext_data {
unsigned int isa_ext_id;
};
-extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
-
-static __always_inline int riscv_isa_ext2key(int num)
-{
- switch (num) {
- case RISCV_ISA_EXT_f:
- return RISCV_ISA_EXT_KEY_FPU;
- case RISCV_ISA_EXT_d:
- return RISCV_ISA_EXT_KEY_FPU;
- case RISCV_ISA_EXT_ZIHINTPAUSE:
- return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
- case RISCV_ISA_EXT_SVINVAL:
- return RISCV_ISA_EXT_KEY_SVINVAL;
- default:
- return -EINVAL;
- }
-}
-
static __always_inline bool
riscv_has_extension_likely(const unsigned long ext)
{
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 50cfbbbecaa7..636dabfd35d0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -29,9 +29,6 @@ unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
-DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
-EXPORT_SYMBOL(riscv_isa_ext_keys);
-
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -266,12 +263,6 @@ void __init riscv_fill_hwcap(void)
if (elf_hwcap & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ELF capabilities %s\n", print_str);
-
- for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
- j = riscv_isa_ext2key(i);
- if (j >= 0)
- static_branch_enable(&riscv_isa_ext_keys[j]);
- }
}
#ifdef CONFIG_RISCV_ALTERNATIVE
--
2.38.1
next prev parent reply other threads:[~2023-01-15 16:03 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-15 15:49 [PATCH v4 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 01/13] riscv: fix jal offsets in patched alternatives Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 04/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2023-01-18 22:28 ` Conor Dooley
2023-01-15 15:49 ` [PATCH v4 06/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2023-01-15 16:29 ` Conor Dooley
2023-01-18 22:18 ` Conor Dooley
2023-01-15 15:49 ` [PATCH v4 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 08/13] riscv: module: move find_section to module.h Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 09/13] riscv: switch to relative alternative entries Jisheng Zhang
2023-01-18 22:11 ` Conor Dooley
2023-01-20 18:34 ` Andrew Jones
2023-01-26 7:09 ` Andrew Jones
2023-01-28 16:43 ` Jisheng Zhang
2023-01-26 19:33 ` Conor Dooley
2023-01-15 15:49 ` [PATCH v4 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang
2023-01-27 3:51 ` Anup Patel
2023-01-15 15:49 ` Jisheng Zhang [this message]
2023-01-25 3:50 ` [PATCH v4 00/13] riscv: improve boot time isa extensions handling patchwork-bot+linux-riscv
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