From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Jisheng Zhang <jszhang@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v4 09/13] riscv: switch to relative alternative entries
Date: Thu, 26 Jan 2023 19:33:28 +0000 [thread overview]
Message-ID: <Y9LViAD0aPSBwi5t@spud> (raw)
In-Reply-To: <20230120183418.ngdppppvwzysqtcr@orel>
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On Fri, Jan 20, 2023 at 07:34:18PM +0100, Andrew Jones wrote:
> On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote:
> ...
> > #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
> > - RISCV_PTR " " oldptr "\n" \
> > - RISCV_PTR " " newptr "\n" \
> > - REG_ASM " " vendor_id "\n" \
> > - REG_ASM " " newlen "\n" \
> > - ".word " errata_id "\n"
> > + ".4byte ((" oldptr ") - .) \n" \
> > + ".4byte ((" newptr ") - .) \n" \
> > + ".2byte " vendor_id "\n" \
> > + ".2byte " newlen "\n" \
> > + ".4byte " errata_id "\n"
> >
>
> Hi Jisheng,
>
> This patch breaks loading the KVM module for me. I got "kvm: Unknown
> relocation type 34". My guess is that these 2 byte fields are inspiring
> the compiler to emit 16-bit relocation types. The patch below fixes
> things for me. If you agree with fixing it this way, rather than
> changing something in alternatives, like not using 2 byte fields,
> then please pick the below patch up in your series.
>
> Thanks,
> drew
>
> From 4d203697aa745a0cd3a9217d547a9fb7fa2a87c7 Mon Sep 17 00:00:00 2001
> From: Andrew Jones <ajones@ventanamicro.com>
> Date: Fri, 20 Jan 2023 19:05:44 +0100
> Subject: [PATCH] riscv: module: Add ADD16 and SUB16 rela types
> Content-type: text/plain
>
> To prepare for 16-bit relocation types to be emitted in alternatives
> add support for ADD16 and SUB16.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
For the fixup:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks!
> ---
> arch/riscv/kernel/module.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
> index 76f4b9c2ec5b..7c651d55fcbd 100644
> --- a/arch/riscv/kernel/module.c
> +++ b/arch/riscv/kernel/module.c
> @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location,
> return -EINVAL;
> }
>
> +static int apply_r_riscv_add16_rela(struct module *me, u32 *location,
> + Elf_Addr v)
> +{
> + *(u16 *)location += (u16)v;
> + return 0;
> +}
> +
> static int apply_r_riscv_add32_rela(struct module *me, u32 *location,
> Elf_Addr v)
> {
> @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location,
> return 0;
> }
>
> +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location,
> + Elf_Addr v)
> +{
> + *(u16 *)location -= (u16)v;
> + return 0;
> +}
> +
> static int apply_r_riscv_sub32_rela(struct module *me, u32 *location,
> Elf_Addr v)
> {
> @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
> [R_RISCV_CALL] = apply_r_riscv_call_rela,
> [R_RISCV_RELAX] = apply_r_riscv_relax_rela,
> [R_RISCV_ALIGN] = apply_r_riscv_align_rela,
> + [R_RISCV_ADD16] = apply_r_riscv_add16_rela,
> [R_RISCV_ADD32] = apply_r_riscv_add32_rela,
> [R_RISCV_ADD64] = apply_r_riscv_add64_rela,
> + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela,
> [R_RISCV_SUB32] = apply_r_riscv_sub32_rela,
> [R_RISCV_SUB64] = apply_r_riscv_sub64_rela,
> };
> --
> 2.39.0
>
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next prev parent reply other threads:[~2023-01-26 19:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-15 15:49 [PATCH v4 00/13] riscv: improve boot time isa extensions handling Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 01/13] riscv: fix jal offsets in patched alternatives Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 02/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 03/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 04/13] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2023-01-18 22:28 ` Conor Dooley
2023-01-15 15:49 ` [PATCH v4 06/13] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2023-01-15 16:29 ` Conor Dooley
2023-01-18 22:18 ` Conor Dooley
2023-01-15 15:49 ` [PATCH v4 07/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 08/13] riscv: module: move find_section to module.h Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 09/13] riscv: switch to relative alternative entries Jisheng Zhang
2023-01-18 22:11 ` Conor Dooley
2023-01-20 18:34 ` Andrew Jones
2023-01-26 7:09 ` Andrew Jones
2023-01-28 16:43 ` Jisheng Zhang
2023-01-26 19:33 ` Conor Dooley [this message]
2023-01-15 15:49 ` [PATCH v4 10/13] riscv: alternative: patch alternatives in the vDSO Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() Jisheng Zhang
2023-01-15 15:49 ` [PATCH v4 12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() Jisheng Zhang
2023-01-27 3:51 ` Anup Patel
2023-01-15 15:49 ` [PATCH v4 13/13] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2023-01-25 3:50 ` [PATCH v4 00/13] riscv: improve boot time isa extensions handling patchwork-bot+linux-riscv
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