From: Brad Larson <blarson@amd.com>
To: <linux-arm-kernel@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <adrian.hunter@intel.com>,
<alcooperx@gmail.com>, <andy.shevchenko@gmail.com>,
<arnd@arndb.de>, <brad@pensando.io>, <blarson@amd.com>,
<brendan.higgins@linux.dev>, <briannorris@chromium.org>,
<brijeshkumar.singh@amd.com>, <catalin.marinas@arm.com>,
<davidgow@google.com>, <gsomlo@gmail.com>, <gerg@linux-m68k.org>,
<krzk@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<lee@kernel.org>, <lee.jones@linaro.org>, <broonie@kernel.org>,
<yamada.masahiro@socionext.com>, <p.zabel@pengutronix.de>,
<piotrs@cadence.com>, <p.yadav@ti.com>, <rdunlap@infradead.org>,
<robh+dt@kernel.org>, <samuel@sholland.org>,
<fancer.lancer@gmail.com>, <skhan@linuxfoundation.org>,
<suravee.suthikulpanit@amd.com>, <thomas.lendacky@amd.com>,
<tonyhuang.sunplus@gmail.com>, <ulf.hansson@linaro.org>,
<vaishnav.a@ti.com>, <will@kernel.org>,
<devicetree@vger.kernel.org>
Subject: [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support
Date: Wed, 18 Jan 2023 19:51:34 -0800 [thread overview]
Message-ID: <20230119035136.21603-14-blarson@amd.com> (raw)
In-Reply-To: <20230119035136.21603-1-blarson@amd.com>
Add support for AMD Pensando Elba SoC which explicitly
controls byte-lane enables on writes.
Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
IO memory accessors.
Signed-off-by: Brad Larson <blarson@amd.com>
---
Changes since v6:
- Previously patch 16/17
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-cadence.c | 131 ++++++++++++++++++++++++++++---
2 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5e19a961c34d..9e41115cc753 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE
tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
depends on MMC_SDHCI_PLTFM
depends on OF
+ select MMC_SDHCI_IO_ACCESSORS
help
This selects the Cadence SD/SDIO/eMMC driver.
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 708d4297f241..e92aa79a8be2 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param {
struct sdhci_cdns_priv {
void __iomem *hrs_addr;
+ void __iomem *ctl_addr; /* write control */
+ spinlock_t wrlock; /* write lock */
bool enhanced_strobe;
void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
unsigned int nr_phy_params;
@@ -77,6 +79,11 @@ struct sdhci_cdns_phy_cfg {
u8 addr;
};
+struct sdhci_cdns_drv_data {
+ int (*init)(struct platform_device *pdev);
+ const struct sdhci_pltfm_data pltfm_data;
+};
+
static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
@@ -316,6 +323,92 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
sdhci_set_uhs_signaling(host, timing);
}
+/* Elba control register bits [6:3] are byte-lane enables */
+#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3)
+
+/*
+ * The Pensando Elba SoC explicitly controls byte-lane enabling on writes
+ * which includes writes to the HRS registers.
+ */
+static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
+ void __iomem *reg)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
+ writel(val, reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
+{
+ elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg);
+}
+
+static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ u32 byte_enables;
+ unsigned long flags;
+
+ byte_enables = GENMASK(1, 0) << (reg & 0x3);
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
+ writew(val, host->ioaddr + reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ u32 byte_enables;
+ unsigned long flags;
+
+ byte_enables = BIT(0) << (reg & 0x3);
+ spin_lock_irqsave(&priv->wrlock, flags);
+ writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
+ writeb(val, host->ioaddr + reg);
+ spin_unlock_irqrestore(&priv->wrlock, flags);
+}
+
+static const struct sdhci_ops sdhci_elba_ops = {
+ .write_l = elba_write_l,
+ .write_w = elba_write_w,
+ .write_b = elba_write_b,
+ .set_clock = sdhci_set_clock,
+ .get_timeout_clock = sdhci_cdns_get_timeout_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = sdhci_reset,
+ .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
+};
+
+static int elba_drv_init(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+ struct resource *iomem;
+ void __iomem *ioaddr;
+
+ host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA);
+
+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!iomem)
+ return -ENOMEM;
+
+ /* Byte-lane control register */
+ ioaddr = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(ioaddr))
+ return PTR_ERR(ioaddr);
+
+ priv->ctl_addr = ioaddr;
+ priv->priv_writel = elba_priv_writel;
+ spin_lock_init(&priv->wrlock);
+ writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
+
+ return 0;
+}
+
static const struct sdhci_ops sdhci_cdns_ops = {
.set_clock = sdhci_set_clock,
.get_timeout_clock = sdhci_cdns_get_timeout_clock,
@@ -325,13 +418,24 @@ static const struct sdhci_ops sdhci_cdns_ops = {
.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
};
-static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
- .ops = &sdhci_cdns_ops,
- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
+ .pltfm_data = {
+ .ops = &sdhci_cdns_ops,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+ },
};
-static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
- .ops = &sdhci_cdns_ops,
+static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
+ .init = elba_drv_init,
+ .pltfm_data = {
+ .ops = &sdhci_elba_ops,
+ },
+};
+
+static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
+ .pltfm_data = {
+ .ops = &sdhci_cdns_ops,
+ },
};
static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
@@ -357,7 +461,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
static int sdhci_cdns_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
- const struct sdhci_pltfm_data *data;
+ const struct sdhci_cdns_drv_data *data;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_cdns_priv *priv;
struct clk *clk;
@@ -376,10 +480,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
data = of_device_get_match_data(dev);
if (!data)
- data = &sdhci_cdns_pltfm_data;
+ data = &sdhci_cdns_drv_data;
nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
- host = sdhci_pltfm_init(pdev, data,
+ host = sdhci_pltfm_init(pdev, &data->pltfm_data,
struct_size(priv, phy_params, nr_phy_params));
if (IS_ERR(host)) {
ret = PTR_ERR(host);
@@ -397,6 +501,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
host->ioaddr += SDHCI_CDNS_SRS_BASE;
host->mmc_host_ops.hs400_enhanced_strobe =
sdhci_cdns_hs400_enhanced_strobe;
+ if (data->init) {
+ ret = data->init(pdev);
+ if (ret)
+ goto free;
+ }
sdhci_enable_v4_mode(host);
__sdhci_read_caps(host, &version, NULL, NULL);
@@ -461,7 +570,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = {
static const struct of_device_id sdhci_cdns_match[] = {
{
.compatible = "socionext,uniphier-sd4hc",
- .data = &sdhci_cdns_uniphier_pltfm_data,
+ .data = &sdhci_cdns_uniphier_drv_data,
+ },
+ {
+ .compatible = "amd,pensando-elba-sd4hc",
+ .data = &sdhci_elba_drv_data,
},
{ .compatible = "cdns,sd4hc" },
{ /* sentinel */ }
--
2.17.1
next prev parent reply other threads:[~2023-01-19 4:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-19 3:51 [PATCH v9 00/15] Support AMD Pensando Elba SoC Brad Larson
2023-01-19 3:51 ` [PATCH v9 01/15] dt-bindings: arm: add AMD Pensando boards Brad Larson
2023-01-19 3:51 ` [PATCH v9 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson
2023-01-19 7:47 ` Krzysztof Kozlowski
2023-01-21 1:10 ` Brad Larson
2023-01-21 18:57 ` Krzysztof Kozlowski
2023-01-19 7:48 ` Krzysztof Kozlowski
2023-01-19 3:51 ` [PATCH v9 03/15] dt-bindings: spi: cdns: Add compatible for " Brad Larson
2023-01-19 7:53 ` Krzysztof Kozlowski
2023-01-24 1:16 ` Brad Larson
2023-01-19 3:51 ` [PATCH v9 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Brad Larson
2023-01-19 7:55 ` Krzysztof Kozlowski
2023-01-24 1:57 ` Brad Larson
2023-01-24 7:22 ` Krzysztof Kozlowski
2023-01-24 21:26 ` Brad Larson
2023-01-19 3:51 ` [PATCH v9 05/15] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Brad Larson
2023-01-19 14:19 ` Lee Jones
2023-01-19 3:51 ` [PATCH v9 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando System Resource chip Brad Larson
2023-01-19 7:58 ` Krzysztof Kozlowski
2023-01-26 2:59 ` Brad Larson
2023-01-19 14:17 ` Lee Jones
2023-01-19 3:51 ` [PATCH v9 07/15] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson
2023-01-19 3:51 ` [PATCH v9 08/15] arm64: Add config for AMD Pensando SoC platforms Brad Larson
2023-01-19 3:51 ` [PATCH v9 09/15] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson
2023-01-19 3:51 ` [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson
2023-01-19 3:51 ` [PATCH v9 11/15] spi: dw: Add support " Brad Larson
2023-01-19 9:58 ` Andy Shevchenko
2023-01-24 2:59 ` Brad Larson
2023-01-19 3:51 ` [PATCH v9 12/15] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson
2023-01-19 3:51 ` Brad Larson [this message]
2023-02-02 9:43 ` [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Adrian Hunter
2023-01-19 3:51 ` [PATCH v9 14/15] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson
2023-01-19 9:34 ` Philipp Zabel
2023-02-07 20:53 ` Brad Larson
2023-01-19 3:51 ` [PATCH v9 15/15] spi: pensando-sr: Add AMD Pensando SoC System Resource Brad Larson
2023-01-19 13:57 ` Mark Brown
2023-02-07 2:12 ` Brad Larson
2023-01-19 12:57 ` [PATCH v9 00/15] Support AMD Pensando Elba SoC Mark Brown
2023-01-24 3:21 ` Brad Larson
-- strict thread matches above, loose matches on Subject: below --
2023-01-19 3:39 Brad Larson
2023-01-19 3:39 ` [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson
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