From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <robh+dt@kernel.org>, <broonie@kernel.org>, <peterhuewe@gmx.de>,
<jgg@ziepe.ca>, <jarkko@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <linux-spi@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-integrity@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<skomatineni@nvidia.com>, <ldewangan@nvidia.com>,
Krishna Yarlagadda <kyarlagadda@nvidia.com>
Subject: [Patch V2 4/4] spi: tegra210-quad: Enable TPM wait polling
Date: Fri, 3 Feb 2023 18:31:33 +0530 [thread overview]
Message-ID: <20230203130133.32901-5-kyarlagadda@nvidia.com> (raw)
In-Reply-To: <20230203130133.32901-1-kyarlagadda@nvidia.com>
Trusted Platform Module defines flow control where slave will drive
data line at specified clock cycles. Tegra241 has TPM wait state
detections support when using combined sequence transfers. Enabling
the feature based on device tree flag.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
drivers/spi/spi-tegra210-quad.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index 9f356612ba7e..ea8a08a3d838 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -142,6 +142,7 @@
#define QSPI_GLOBAL_CONFIG 0X1a4
#define QSPI_CMB_SEQ_EN BIT(0)
+#define QSPI_TPM_WAIT_POLL_EN BIT(1)
#define QSPI_CMB_SEQ_ADDR 0x1a8
#define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0)
@@ -170,6 +171,7 @@ struct tegra_qspi_soc_data {
struct tegra_qspi_client_data {
int tx_clk_tap_delay;
int rx_clk_tap_delay;
+ bool wait_polling;
};
struct tegra_qspi {
@@ -934,6 +936,8 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic
&cdata->tx_clk_tap_delay);
device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
&cdata->rx_clk_tap_delay);
+ cdata->wait_polling =
+ device_property_read_bool(&spi->dev, "nvidia,wait-polling");
return cdata;
}
@@ -991,6 +995,14 @@ static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi)
dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS),
tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS));
+ dev_dbg(tqspi->dev, "GLOBAL_CFG: 0x%08x\n",
+ tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG));
+ dev_dbg(tqspi->dev, "CMB_CMD: 0x%08x | CMB_CMD_CFG: 0x%08x\n",
+ tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD),
+ tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD_CFG));
+ dev_dbg(tqspi->dev, "CMB_ADDR: 0x%08x | CMB_ADDR_CFG: 0x%08x\n",
+ tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR),
+ tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR_CFG));
}
static void tegra_qspi_handle_error(struct tegra_qspi *tqspi)
@@ -1056,6 +1068,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
bool is_first_msg = true;
struct spi_transfer *xfer;
struct spi_device *spi = msg->spi;
+ struct tegra_qspi_client_data *cdata = spi->controller_data;
u8 transfer_phase = 0;
u32 cmd1 = 0, dma_ctl = 0;
int ret = 0;
@@ -1065,6 +1078,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
/* Enable Combined sequence mode */
val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
+ if (cdata->wait_polling)
+ val |= QSPI_TPM_WAIT_POLL_EN;
val |= QSPI_CMB_SEQ_EN;
tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
/* Process individual transfer list */
@@ -1192,6 +1207,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
/* Disable Combined sequence mode */
val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
val &= ~QSPI_CMB_SEQ_EN;
+ val &= ~QSPI_TPM_WAIT_POLL_EN;
tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
struct spi_transfer *xfer = transfer;
--
2.17.1
prev parent reply other threads:[~2023-02-03 13:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 13:01 [Patch V2 0/4] Tegra TPM driver with hw flow control Krishna Yarlagadda
2023-02-03 13:01 ` [Patch V2 1/4] dt-bindings: tpm: Add compatible for Tegra TPM Krishna Yarlagadda
2023-02-03 18:57 ` Rob Herring
2023-02-03 13:01 ` [Patch V2 2/4] tpm: tegra: Support SPI tpm wait state detect Krishna Yarlagadda
2023-02-03 23:43 ` kernel test robot
2023-02-04 9:48 ` kernel test robot
2023-02-06 11:02 ` Paul Menzel
2023-02-06 13:19 ` Mark Brown
2023-02-06 16:10 ` Thierry Reding
2023-02-03 13:01 ` [Patch V2 3/4] spi: dt-bindings: Add Tegra TPM wait polling flag Krishna Yarlagadda
2023-02-03 19:49 ` Rob Herring
2023-02-23 16:26 ` Krishna Yarlagadda
2023-02-03 13:01 ` Krishna Yarlagadda [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230203130133.32901-5-kyarlagadda@nvidia.com \
--to=kyarlagadda@nvidia.com \
--cc=broonie@kernel.org \
--cc=jarkko@kernel.org \
--cc=jgg@ziepe.ca \
--cc=jonathanh@nvidia.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=ldewangan@nvidia.com \
--cc=linux-integrity@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=peterhuewe@gmx.de \
--cc=robh+dt@kernel.org \
--cc=skomatineni@nvidia.com \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).