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* [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers
@ 2023-02-25  9:42 Yassine Oudjana
  2023-02-25  9:42 ` [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings Yassine Oudjana
                   ` (3 more replies)
  0 siblings, 4 replies; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-25  9:42 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel

From: Yassine Oudjana <y.oudjana@protonmail.com>

These patches are part of a larger effort to support the MT6735 SoC family in mainline
Linux. More patches (unsent or sent and pending review or revision) can be found here[1].

This series adds support for the main clock and reset controllers on the
Mediatek MT6735 SoC:
- apmixedsys (global PLLs)
- topckgen (global divisors and muxes)
- infracfg (gates and resets for internal components)
- pericfg (gates and resets for peripherals)

MT6735 has other more specialized clock/reset controllers, support for which is
not included in this series:
- mfgcfg (GPU)
- imgsys (camera)
- mmsys (display)
- vdecsys (video decoder)
- vencsys (video encoder)
- audsys (audio)

Changes since v2:
- Add "CLK_" prefix to infracfg and pericfg clock definitions to avoid possible
  clashes with reset bindings.
- Replace "_RST" suffix with "RST_" prefix to maintain consistency with clock bindings.
- Use macros to define clocks.
- Abandon mtk_clk_simple_probe/mtk_clk_simple_remove in favor of custom functions in apmixedsys
  and topckgen drivers for the time being. 
- Capitalize T in MediaTek in MODULE_DESCRIPTION.
Changes since v1:
- Rebase on some pending patches.
- Move common clock improvements to a separate series.
- Use mtk_clk_simple_probe/remove after making them support several clock types
  in said series.
- Combine all 4 drivers into one patch, and use one Kconfig symbol for all
  following a conversation seen on a different series[2].
- Correct APLL2 registers in apmixedsys driver (were offset backwards by 0x4).
- Make irtx clock name lower case to match the other clocks.

[1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging
[2] https://lore.kernel.org/linux-mediatek/CAGXv+5H4gF5GXzfk8mjkG4Kry8uCs1CQbKoViBuc9LC+XdHH=A@mail.gmail.com/

Yassine Oudjana (4):
  dt-bindings: clock: Add MediaTek MT6735 clock bindings
  dt-bindings: reset: Add MediaTek MT6735 reset bindings
  dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
  clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset
    drivers

 .../arm/mediatek/mediatek,infracfg.yaml       |   8 +-
 .../arm/mediatek/mediatek,pericfg.yaml        |   1 +
 .../bindings/clock/mediatek,apmixedsys.yaml   |   4 +-
 .../bindings/clock/mediatek,topckgen.yaml     |   4 +-
 MAINTAINERS                                   |  16 +
 drivers/clk/mediatek/Kconfig                  |   9 +
 drivers/clk/mediatek/Makefile                 |   1 +
 drivers/clk/mediatek/clk-mt6735-apmixedsys.c  | 139 ++++++
 drivers/clk/mediatek/clk-mt6735-infracfg.c    |  78 +++
 drivers/clk/mediatek/clk-mt6735-pericfg.c     |  91 ++++
 drivers/clk/mediatek/clk-mt6735-topckgen.c    | 450 ++++++++++++++++++
 .../clock/mediatek,mt6735-apmixedsys.h        |  16 +
 .../clock/mediatek,mt6735-infracfg.h          |  25 +
 .../clock/mediatek,mt6735-pericfg.h           |  37 ++
 .../clock/mediatek,mt6735-topckgen.h          |  79 +++
 .../reset/mediatek,mt6735-infracfg.h          |  31 ++
 .../reset/mediatek,mt6735-pericfg.h           |  31 ++
 17 files changed, 1015 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h

-- 
2.39.2


^ permalink raw reply	[flat|nested] 15+ messages in thread
* [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings
  2023-02-25  9:42 [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers Yassine Oudjana
@ 2023-02-25  9:42 ` Yassine Oudjana
  2023-02-27  8:18   ` Krzysztof Kozlowski
  2023-02-25  9:42 ` [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings Yassine Oudjana
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-25  9:42 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel, Rob Herring

From: Yassine Oudjana <y.oudjana@protonmail.com>

Add clock definitions for the main clock controllers of MT6735 (apmixedsys,
topckgen, infracfg and pericfg).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 MAINTAINERS                                   | 10 +++
 .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
 .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
 .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
 .../clock/mediatek,mt6735-topckgen.h          | 79 +++++++++++++++++++
 5 files changed, 167 insertions(+)
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e2a35aebba0c..5323f71c48fb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13101,6 +13101,16 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/mmc/mtk-sd.yaml
 F:	drivers/mmc/host/mtk-sd.c
 
+MEDIATEK MT6735 CLOCK DRIVERS
+M:	Yassine Oudjana <y.oudjana@protonmail.com>
+L:	linux-clk@vger.kernel.org
+L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
+F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h
+F:	include/dt-bindings/clock/mediatek,mt6735-pericfg.h
+F:	include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+
 MEDIATEK MT76 WIRELESS LAN DRIVER
 M:	Felix Fietkau <nbd@nbd.name>
 M:	Lorenzo Bianconi <lorenzo@kernel.org>
diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
new file mode 100644
index 000000000000..3dda719fd5d5
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+
+#define ARMPLL				0
+#define MAINPLL				1
+#define UNIVPLL				2
+#define MMPLL				3
+#define MSDCPLL				4
+#define VENCPLL				5
+#define TVDPLL				6
+#define APLL1				7
+#define APLL2				8
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..a42be76c778d
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+
+#define CLK_DBG				0
+#define CLK_GCE				1
+#define CLK_TRBG			2
+#define CLK_CPUM			3
+#define CLK_DEVAPC			4
+#define CLK_AUDIO			5
+#define CLK_GCPU			6
+#define CLK_L2C_SRAM			7
+#define CLK_M4U				8
+#define CLK_CLDMA			9
+#define CLK_CONNMCU_BUS			10
+#define CLK_KP				11
+#define CLK_APXGPT			12
+#define CLK_SEJ				13
+#define CLK_CCIF0_AP			14
+#define CLK_CCIF1_AP			15
+#define CLK_PMIC_SPI			16
+#define CLK_PMIC_WRAP			17
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..72401f009176
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H
+#define _DT_BINDINGS_CLK_MT6735_PERICFG_H
+
+#define CLK_DISP_PWM			0
+#define CLK_THERM			1
+#define CLK_PWM1			2
+#define CLK_PWM2			3
+#define CLK_PWM3			4
+#define CLK_PWM4			5
+#define CLK_PWM5			6
+#define CLK_PWM6			7
+#define CLK_PWM7			8
+#define CLK_PWM				9
+#define CLK_USB0			10
+#define CLK_IRDA			11
+#define CLK_APDMA			12
+#define CLK_MSDC30_0			13
+#define CLK_MSDC30_1			14
+#define CLK_MSDC30_2			15
+#define CLK_MSDC30_3			16
+#define CLK_UART0			17
+#define CLK_UART1			18
+#define CLK_UART2			19
+#define CLK_UART3			20
+#define CLK_UART4			21
+#define CLK_BTIF			22
+#define CLK_I2C0			23
+#define CLK_I2C1			24
+#define CLK_I2C2			25
+#define CLK_I2C3			26
+#define CLK_AUXADC			27
+#define CLK_SPI0			28
+#define CLK_IRTX			29
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
new file mode 100644
index 000000000000..a771910a4b8a
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+
+#define AD_SYS_26M_CK			0
+#define CLKPH_MCK_O			1
+#define DMPLL				2
+#define DPI_CK				3
+#define WHPLL_AUDIO_CK			4
+
+#define SYSPLL_D2			5
+#define SYSPLL_D3			6
+#define SYSPLL_D5			7
+#define SYSPLL1_D2			8
+#define SYSPLL1_D4			9
+#define SYSPLL1_D8			10
+#define SYSPLL1_D16			11
+#define SYSPLL2_D2			12
+#define SYSPLL2_D4			13
+#define SYSPLL3_D2			14
+#define SYSPLL3_D4			15
+#define SYSPLL4_D2			16
+#define SYSPLL4_D4			17
+#define UNIVPLL_D2			18
+#define UNIVPLL_D3			19
+#define UNIVPLL_D5			20
+#define UNIVPLL_D26			21
+#define UNIVPLL1_D2			22
+#define UNIVPLL1_D4			23
+#define UNIVPLL1_D8			24
+#define UNIVPLL2_D2			25
+#define UNIVPLL2_D4			26
+#define UNIVPLL2_D8			27
+#define UNIVPLL3_D2			28
+#define UNIVPLL3_D4			29
+#define MSDCPLL_D2			30
+#define MSDCPLL_D4			31
+#define MSDCPLL_D8			32
+#define MSDCPLL_D16			33
+#define VENCPLL_D3			34
+#define TVDPLL_D2			35
+#define TVDPLL_D4			36
+#define DMPLL_D2			37
+#define DMPLL_D4			38
+#define DMPLL_D8			39
+#define AD_SYS_26M_D2			40
+
+#define AXI_SEL				41
+#define MEM_SEL				42
+#define DDRPHY_SEL			43
+#define MM_SEL				44
+#define PWM_SEL				45
+#define VDEC_SEL			46
+#define MFG_SEL				47
+#define CAMTG_SEL			48
+#define UART_SEL			49
+#define SPI_SEL				50
+#define USB20_SEL			51
+#define MSDC50_0_SEL			52
+#define MSDC30_0_SEL			53
+#define MSDC30_1_SEL			54
+#define MSDC30_2_SEL			55
+#define MSDC30_3_SEL			56
+#define AUDIO_SEL			57
+#define AUDINTBUS_SEL			58
+#define PMICSPI_SEL			59
+#define SCP_SEL				60
+#define ATB_SEL				61
+#define DPI0_SEL			62
+#define SCAM_SEL			63
+#define MFG13M_SEL			64
+#define AUD1_SEL			65
+#define AUD2_SEL			66
+#define IRDA_SEL			67
+#define IRTX_SEL			68
+#define DISPPWM_SEL			69
+
+#endif
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings
  2023-02-25  9:42 [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  2023-02-25  9:42 ` [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings Yassine Oudjana
@ 2023-02-25  9:42 ` Yassine Oudjana
  2023-02-27  8:17   ` Krzysztof Kozlowski
  2023-02-25  9:42 ` [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
  2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  3 siblings, 1 reply; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-25  9:42 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel, Rob Herring

From: Yassine Oudjana <y.oudjana@protonmail.com>

Add reset definitions for the main reset controllers of MT6735 (infracfg
and pericfg).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 MAINTAINERS                                   |  4 ++-
 .../reset/mediatek,mt6735-infracfg.h          | 31 +++++++++++++++++++
 .../reset/mediatek,mt6735-pericfg.h           | 31 +++++++++++++++++++
 3 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5323f71c48fb..f617042790ee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13101,7 +13101,7 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/mmc/mtk-sd.yaml
 F:	drivers/mmc/host/mtk-sd.c
 
-MEDIATEK MT6735 CLOCK DRIVERS
+MEDIATEK MT6735 CLOCK & RESET DRIVERS
 M:	Yassine Oudjana <y.oudjana@protonmail.com>
 L:	linux-clk@vger.kernel.org
 L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
@@ -13110,6 +13110,8 @@ F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h
 F:	include/dt-bindings/clock/mediatek,mt6735-pericfg.h
 F:	include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F:	include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F:	include/dt-bindings/reset/mediatek,mt6735-pericfg.h
 
 MEDIATEK MT76 WIRELESS LAN DRIVER
 M:	Felix Fietkau <nbd@nbd.name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..5d24c7a1317f
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+
+#define RST_EMI_REG			0
+#define RST_DRAMC0_AO			1
+#define RST_AP_CIRQ_EINT		3
+#define RST_APXGPT			4
+#define RST_SCPSYS			5
+#define RST_KP				6
+#define RST_PMIC_WRAP			7
+#define RST_CLDMA_AO_TOP		8
+#define RST_EMI				16
+#define RST_CCIF			17
+#define RST_DRAMC0			18
+#define RST_EMI_AO_REG			19
+#define RST_CCIF_AO			20
+#define RST_TRNG			21
+#define RST_SYS_CIRQ			22
+#define RST_GCE				23
+#define RST_M4U				24
+#define RST_CCIF1			25
+#define RST_CLDMA_TOP_PD		26
+#define RST_CBIP_P2P_MFG		27
+#define RST_CBIP_P2P_APMIXED		28
+#define RST_CBIP_P2P_CKSYS		29
+#define RST_CBIP_P2P_MIPI		30
+#define RST_CBIP_P2P_DDRPHY		31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..90ee8ed8923f
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H
+#define _DT_BINDINGS_RESET_MT6735_PERICFG_H
+
+#define RST_UART0			0
+#define RST_UART1			1
+#define RST_UART2			2
+#define RST_UART3			3
+#define RST_UART4			4
+#define RST_BTIF			6
+#define RST_DISP_PWM_PERI		7
+#define RST_PWM				8
+#define RST_AUXADC			10
+#define RST_DMA				11
+#define RST_IRDA			12
+#define RST_IRTX			13
+#define RST_THERM			16
+#define RST_MSDC2			17
+#define RST_MSDC3			17
+#define RST_MSDC0			19
+#define RST_MSDC1			20
+#define RST_I2C0			22
+#define RST_I2C1			23
+#define RST_I2C2			24
+#define RST_I2C3			25
+#define RST_USB				28
+
+#define RST_SPI0			33
+
+#endif
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
  2023-02-25  9:42 [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  2023-02-25  9:42 ` [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings Yassine Oudjana
  2023-02-25  9:42 ` [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings Yassine Oudjana
@ 2023-02-25  9:42 ` Yassine Oudjana
  2023-02-27  8:18   ` Krzysztof Kozlowski
  2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  3 siblings, 1 reply; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-25  9:42 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel, Rob Herring

From: Yassine Oudjana <y.oudjana@protonmail.com>

Add compatible strings for MT6735 apmixedsys, topckgen, infracfg
and pericfg.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/arm/mediatek/mediatek,infracfg.yaml          | 8 +++++---
 .../bindings/arm/mediatek/mediatek,pericfg.yaml           | 1 +
 .../devicetree/bindings/clock/mediatek,apmixedsys.yaml    | 4 +++-
 .../devicetree/bindings/clock/mediatek,topckgen.yaml      | 4 +++-
 4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
index e997635e4fe4..715e24a4ddda 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -11,9 +11,10 @@ maintainers:
 
 description:
   The Mediatek infracfg controller provides various clocks and reset outputs
-  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
-  and reset values in <dt-bindings/reset/mt*-reset.h> and
-  <dt-bindings/reset/mt*-resets.h>.
+  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+  and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
+  <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
+  <dt-bindings/reset/mediatek,mt*-infracfg.h>.
 
 properties:
   compatible:
@@ -22,6 +23,7 @@ properties:
           - enum:
               - mediatek,mt2701-infracfg
               - mediatek,mt2712-infracfg
+              - mediatek,mt6735-infracfg
               - mediatek,mt6765-infracfg
               - mediatek,mt6795-infracfg
               - mediatek,mt6779-infracfg_ao
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index ef62cbb13590..fd2f97973264 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -20,6 +20,7 @@ properties:
           - enum:
               - mediatek,mt2701-pericfg
               - mediatek,mt2712-pericfg
+              - mediatek,mt6735-pericfg
               - mediatek,mt6765-pericfg
               - mediatek,mt6795-pericfg
               - mediatek,mt7622-pericfg
diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
index dae25dba4ba6..73512038b27c 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
@@ -12,7 +12,8 @@ maintainers:
 
 description:
   The Mediatek apmixedsys controller provides PLLs to the system.
-  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+  The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+  and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
 
 properties:
   compatible:
@@ -33,6 +34,7 @@ properties:
           - enum:
               - mediatek,mt2701-apmixedsys
               - mediatek,mt2712-apmixedsys
+              - mediatek,mt6735-apmixedsys
               - mediatek,mt6765-apmixedsys
               - mediatek,mt6779-apmixedsys
               - mediatek,mt6795-apmixedsys
diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
index 0fdf56414833..a580ad03a5bf 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
@@ -12,7 +12,8 @@ maintainers:
 
 description:
   The Mediatek topckgen controller provides various clocks to the system.
-  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+  The clock values can be found in <dt-bindings/clock/mt*-clk.h> and
+  <dt-bindings/clock/mediatek,mt*-topckgen.h>.
 
 properties:
   compatible:
@@ -31,6 +32,7 @@ properties:
           - enum:
               - mediatek,mt2701-topckgen
               - mediatek,mt2712-topckgen
+              - mediatek,mt6735-topckgen
               - mediatek,mt6765-topckgen
               - mediatek,mt6779-topckgen
               - mediatek,mt6795-topckgen
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-25  9:42 [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers Yassine Oudjana
                   ` (2 preceding siblings ...)
  2023-02-25  9:42 ` [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
@ 2023-02-25  9:42 ` Yassine Oudjana
  2023-02-25 12:05   ` kernel test robot
                     ` (2 more replies)
  3 siblings, 3 replies; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-25  9:42 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel

From: Yassine Oudjana <y.oudjana@protonmail.com>

Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
clock and reset controllers. These provide the base clocks and resets
on the platform, and should be enough to bring up all essential blocks
including PWRAP, MSDC and peripherals (UART, I2C, SPI).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
 MAINTAINERS                                  |   4 +
 drivers/clk/mediatek/Kconfig                 |   9 +
 drivers/clk/mediatek/Makefile                |   1 +
 drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++
 drivers/clk/mediatek/clk-mt6735-infracfg.c   |  78 ++++
 drivers/clk/mediatek/clk-mt6735-pericfg.c    |  91 ++++
 drivers/clk/mediatek/clk-mt6735-topckgen.c   | 450 +++++++++++++++++++
 7 files changed, 772 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c

diff --git a/MAINTAINERS b/MAINTAINERS
index f617042790ee..d7ec4a36a934 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13106,6 +13106,10 @@ M:	Yassine Oudjana <y.oudjana@protonmail.com>
 L:	linux-clk@vger.kernel.org
 L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
+F:	drivers/clk/mediatek/clk-mt6735-apmixedsys.c
+F:	drivers/clk/mediatek/clk-mt6735-infracfg.c
+F:	drivers/clk/mediatek/clk-mt6735-pericfg.c
+F:	drivers/clk/mediatek/clk-mt6735-topckgen.c
 F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h
 F:	include/dt-bindings/clock/mediatek,mt6735-pericfg.h
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2d14855dd37e..593791c0a7d6 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -124,6 +124,15 @@ config COMMON_CLK_MT2712_VENCSYS
 	help
 	  This driver supports MediaTek MT2712 vencsys clocks.
 
+config COMMON_CLK_MT6735
+	tristate "Main clock drivers for MediaTek MT6735"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	select COMMON_CLK_MEDIATEK
+	help
+	  This enables drivers for clocks and resets provided
+	  by apmixedsys, topckgen, infracfg and pericfg on the
+	  MediaTek MT6735 SoC.
+
 config COMMON_CLK_MT6765
        bool "Clock driver for MediaTek MT6765"
        depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e5d018270ed0..d2496a8d0467 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
 
+obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
new file mode 100644
index 000000000000..5ce395c34d92
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
+
+#define AP_PLL_CON_5		0x014
+#define ARMPLL_CON0		0x200
+#define ARMPLL_CON1		0x204
+#define ARMPLL_PWR_CON0		0x20c
+#define MAINPLL_CON0		0x210
+#define MAINPLL_CON1		0x214
+#define MAINPLL_PWR_CON0	0x21c
+#define UNIVPLL_CON0		0x220
+#define UNIVPLL_CON1		0x224
+#define UNIVPLL_PWR_CON0	0x22c
+#define MMPLL_CON0		0x230
+#define MMPLL_CON1		0x234
+#define MMPLL_PWR_CON0		0x23c
+#define MSDCPLL_CON0		0x240
+#define MSDCPLL_CON1		0x244
+#define MSDCPLL_PWR_CON0	0x24c
+#define VENCPLL_CON0		0x250
+#define VENCPLL_CON1		0x254
+#define VENCPLL_PWR_CON0	0x25c
+#define TVDPLL_CON0		0x260
+#define TVDPLL_CON1		0x264
+#define TVDPLL_PWR_CON0		0x26c
+#define APLL1_CON0		0x270
+#define APLL1_CON1		0x274
+#define APLL1_CON2		0x278
+#define APLL1_PWR_CON0		0x280
+#define APLL2_CON0		0x284
+#define APLL2_CON1		0x288
+#define APLL2_CON2		0x28c
+#define APLL2_PWR_CON0		0x294
+
+#define CON0_RST_BAR		BIT(24)
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask,	\
+	    _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,		\
+	    _tuner_en_bit, _pcw_reg, _pcwbits, _flags) {		\
+		.id = _id,						\
+		.name = _name,						\
+		.parent_name = "clk26m",				\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = _rst_bar_mask,				\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.tuner_reg = _tuner_reg,				\
+		.tuner_en_reg = _tuner_en_reg,				\
+		.tuner_en_bit = _tuner_en_bit,				\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_chg_reg = _pcw_reg,				\
+		.pcwbits = _pcwbits,					\
+		.flags = _flags,					\
+	}
+
+static const struct mtk_pll_data apmixedsys_plls[] = {
+	PLL(ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO),
+	PLL(MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_RST_BAR),
+	PLL(UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_RST_BAR),
+	PLL(MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
+	PLL(MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 24, 0, 0, 0, MSDCPLL_CON1, 21, 0),
+	PLL(VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENCPLL_CON1, 24, 0, 0, 0, VENCPLL_CON1, 21, HAVE_RST_BAR),
+	PLL(TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0, 0, 0, TVDPLL_CON1, 21, 0),
+	PLL(APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CON2, AP_PLL_CON_5, 0, APLL1_CON1, 31, 0),
+	PLL(APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
+};
+
+int clk_mt6735_apmixed_probe(struct platform_device *pdev)
+{
+	void __iomem *base;
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	struct clk_hw_onecell_data *clk_data;
+	int ret;
+
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixedsys_plls));
+	if (!clk_data)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, clk_data);
+
+	ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
+				   ARRAY_SIZE(apmixedsys_plls), clk_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
+		return ret;
+	}
+
+	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+					  clk_data);
+	if (ret)
+		dev_err(&pdev->dev,
+			"Failed to register clock provider: %d\n", ret);
+
+	return ret;
+}
+
+int clk_mt6735_apmixed_remove(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+	mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
+	mtk_free_clk_data(clk_data);
+
+	return 0;
+}
+
+static const struct of_device_id of_match_mt6735_apmixedsys[] = {
+	{ .compatible = "mediatek,mt6735-apmixedsys" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_apmixedsys = {
+	.probe = clk_mt6735_apmixed_probe,
+	.remove = clk_mt6735_apmixed_remove,
+	.driver = {
+		.name = "clk-mt6735-apmixedsys",
+		.of_match_table = of_match_mt6735_apmixedsys,
+	},
+};
+module_platform_driver(clk_mt6735_apmixedsys);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 apmixedsys clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/mediatek/clk-mt6735-infracfg.c
new file mode 100644
index 000000000000..e9dd3caa5f97
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
+
+#define INFRA_RST0			0x30
+#define INFRA_GLOBALCON_PDN0		0x40
+#define INFRA_PDN1			0x44
+#define	INFRA_PDN_STA			0x48
+
+static struct mtk_gate_regs infra_cg_regs = {
+	.set_ofs = INFRA_GLOBALCON_PDN0,
+	.clr_ofs = INFRA_PDN1,
+	.sta_ofs = INFRA_PDN_STA,
+};
+
+static const struct mtk_gate infracfg_gates[] = {
+	GATE_MTK(CLK_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
+	GATE_MTK_FLAGS(CLK_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
+	GATE_MTK(CLK_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
+};
+
+static u16 infracfg_rst_ofs[] = { INFRA_RST0 };
+
+static const struct mtk_clk_rst_desc infracfg_resets = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = infracfg_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infracfg_rst_ofs)
+};
+
+static const struct mtk_clk_desc infracfg_clks = {
+	.clks = infracfg_gates,
+	.num_clks = ARRAY_SIZE(infracfg_gates),
+
+	.rst_desc = &infracfg_resets
+};
+
+static const struct of_device_id of_match_mt6735_infracfg[] = {
+	{ .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_infracfg = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6735-infracfg",
+		.of_match_table = of_match_mt6735_infracfg,
+	},
+};
+module_platform_driver(clk_mt6735_infracfg);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediatek/clk-mt6735-pericfg.c
new file mode 100644
index 000000000000..4d74e345509b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-pericfg.h>
+
+#define PERI_GLOBALCON_RST0		0x00
+#define PERI_GLOBALCON_RST1		0x04
+#define PERI_GLOBALCON_PDN0_SET		0x08
+#define PERI_GLOBALCON_PDN0_CLR		0x10
+#define	PERI_GLOBALCON_PDN0_STA		0x18
+
+static struct mtk_gate_regs peri_cg_regs = {
+	.set_ofs = PERI_GLOBALCON_PDN0_SET,
+	.clr_ofs = PERI_GLOBALCON_PDN0_CLR,
+	.sta_ofs = PERI_GLOBALCON_PDN0_STA,
+};
+
+static const struct mtk_gate pericfg_gates[] = {
+	GATE_MTK(CLK_DISP_PWM, "disp_pwm", "disppwm_sel", &peri_cg_regs, 0, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_THERM, "therm", "axi_sel", &peri_cg_regs, 1, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_PWM, "pwm", "axi_sel", &peri_cg_regs, 9, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_USB0, "usb0", "usb20_sel", &peri_cg_regs, 10, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_IRDA, "irda", "irda_sel", &peri_cg_regs, 11, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_MSDC30_0, "msdc30_0", "msdc30_0_sel", &peri_cg_regs, 13, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_MSDC30_1, "msdc30_1", "msdc30_1_sel", &peri_cg_regs, 14, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_MSDC30_2, "msdc30_2", "msdc30_2_sel", &peri_cg_regs, 15, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_MSDC30_3, "msdc30_3", "msdc30_3_sel", &peri_cg_regs, 16, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_UART1, "uart1", "uart_sel", &peri_cg_regs, 18, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_UART3, "uart3", "uart_sel", &peri_cg_regs, 20, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_UART4, "uart4", "uart_sel", &peri_cg_regs, 21, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_BTIF, "btif", "axi_sel", &peri_cg_regs, 22, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_I2C0, "i2c0", "axi_sel", &peri_cg_regs, 23, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_I2C1, "i2c1", "axi_sel", &peri_cg_regs, 24, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_I2C2, "i2c2", "axi_sel", &peri_cg_regs, 25, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_I2C3, "i2c3", "axi_sel", &peri_cg_regs, 26, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_AUXADC, "auxadc", "axi_sel", &peri_cg_regs, 27, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_SPI0, "spi0", "spi_sel", &peri_cg_regs, 28, &mtk_clk_gate_ops_setclr),
+	GATE_MTK(CLK_IRTX, "irtx", "irtx_sel", &peri_cg_regs, 29, &mtk_clk_gate_ops_setclr)
+};
+
+static u16 pericfg_rst_ofs[] = { PERI_GLOBALCON_RST0, PERI_GLOBALCON_RST1 };
+
+static const struct mtk_clk_rst_desc pericfg_resets = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = pericfg_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs)
+};
+
+static const struct mtk_clk_desc pericfg_clks = {
+	.clks = pericfg_gates,
+	.num_clks = ARRAY_SIZE(pericfg_gates),
+
+	.rst_desc = &pericfg_resets
+};
+
+static const struct of_device_id of_match_mt6735_pericfg[] = {
+	{ .compatible = "mediatek,mt6735-pericfg", .data = &pericfg_clks },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_pericfg = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6735-pericfg",
+		.of_match_table = of_match_mt6735_pericfg,
+	},
+};
+module_platform_driver(clk_mt6735_pericfg);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 pericfg clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/mediatek/clk-mt6735-topckgen.c
new file mode 100644
index 000000000000..5fa743e4b0fc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
+
+#define CLK_CFG_0		0x40
+#define CLK_CFG_0_SET		0x44
+#define CLK_CFG_0_CLR		0x48
+#define CLK_CFG_1		0x50
+#define CLK_CFG_1_SET		0x54
+#define CLK_CFG_1_CLR		0x58
+#define CLK_CFG_2		0x60
+#define CLK_CFG_2_SET		0x64
+#define CLK_CFG_2_CLR		0x68
+#define CLK_CFG_3		0x70
+#define CLK_CFG_3_SET		0x74
+#define CLK_CFG_3_CLR		0x78
+#define CLK_CFG_4		0x80
+#define CLK_CFG_4_SET		0x84
+#define CLK_CFG_4_CLR		0x88
+#define CLK_CFG_5		0x90
+#define CLK_CFG_5_SET		0x94
+#define CLK_CFG_5_CLR		0x98
+#define CLK_CFG_6		0xa0
+#define CLK_CFG_6_SET		0xa4
+#define CLK_CFG_6_CLR		0xa8
+#define CLK_CFG_7		0xb0
+#define CLK_CFG_7_SET		0xb4
+#define CLK_CFG_7_CLR		0xb8
+
+static DEFINE_SPINLOCK(mt6735_topckgen_lock);
+
+/* Some clocks with unknown details are modeled as fixed clocks */
+static const struct mtk_fixed_clk topckgen_fixed_clks[] = {
+	/*
+	 * This clock is available as a parent option for multiple
+	 * muxes and seems like an alternative name for clk26m at first,
+	 * but it appears alongside it in several muxes which should
+	 * mean it is a separate clock.
+	 */
+	FIXED_CLK(AD_SYS_26M_CK, "ad_sys_26m_ck", "clk26m", 26 * MHZ),
+	/*
+	 * This clock is the parent of DMPLL divisors. It might be MEMPLL
+	 * or its parent, as DMPLL appears to be an alternative name for
+	 * MEMPLL.
+	 */
+	FIXED_CLK(CLKPH_MCK_O, "clkph_mck_o", NULL, 0),
+	/*
+	 * DMPLL clock (dmpll_ck), controlled by DDRPHY.
+	 */
+	FIXED_CLK(DMPLL, "dmpll", "clkph_mck_o", 0),
+	/*
+	 * MIPI DPI clock. Parent option for dpi0_sel. Unknown parent.
+	 */
+	FIXED_CLK(DPI_CK, "dpi_ck", NULL, 0),
+	/*
+	 * This clock is a child of WHPLL which is controlled by
+	 * the modem.
+	 */
+	FIXED_CLK(WHPLL_AUDIO_CK, "whpll_audio_ck", NULL, 0)
+};
+
+static const struct mtk_fixed_factor topckgen_factors[] = {
+	FACTOR(SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
+	FACTOR(SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
+	FACTOR(SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
+	FACTOR(SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 2),
+	FACTOR(SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 4),
+	FACTOR(SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 8),
+	FACTOR(SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 16),
+	FACTOR(SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 2),
+	FACTOR(SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 4),
+	FACTOR(SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 2),
+	FACTOR(SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 4),
+	FACTOR(SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 2),
+	FACTOR(SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 4),
+	FACTOR(UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+	FACTOR(UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+	FACTOR(UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+	FACTOR(UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
+	FACTOR(UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 2),
+	FACTOR(UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 4),
+	FACTOR(UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 8),
+	FACTOR(UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
+	FACTOR(UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
+	FACTOR(UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
+	FACTOR(UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 2),
+	FACTOR(UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 4),
+	FACTOR(MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+	FACTOR(MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
+	FACTOR(MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
+	FACTOR(MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
+	FACTOR(VENCPLL_D3, "vencpll_d3", "vencpll", 1, 3),
+	FACTOR(TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
+	FACTOR(TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
+	FACTOR(DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
+	FACTOR(DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
+	FACTOR(DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
+	FACTOR(AD_SYS_26M_D2, "ad_sys_26m_d2", "clk26m", 1, 2)
+};
+
+static const char * const axi_sel_parents[] = {
+	"clk26m",
+	"syspll1_d2",
+	"syspll_d5",
+	"syspll1_d4",
+	"univpll_d5",
+	"univpll2_d2",
+	"dmpll",
+	"dmpll_d2"
+};
+
+static const char * const mem_sel_parents[] = {
+	"clk26m",
+	"dmpll"
+};
+
+static const char * const ddrphycfg_parents[] = {
+	"clk26m",
+	"syspll1_d8"
+};
+
+static const char * const mm_sel_parents[] = {
+	"clk26m",
+	"vencpll",
+	"syspll1_d2",
+	"syspll_d5",
+	"syspll1_d4",
+	"univpll_d5",
+	"univpll2_d2",
+	"dmpll"
+};
+
+static const char * const pwm_sel_parents[] = {
+	"clk26m",
+	"univpll2_d4",
+	"univpll3_d2",
+	"univpll1_d4"
+};
+
+static const char * const vdec_sel_parents[] = {
+	"clk26m",
+	"syspll1_d2",
+	"syspll_d5",
+	"syspll1_d4",
+	"univpll_d5",
+	"syspll_d2",
+	"syspll2_d2",
+	"msdcpll_d2"
+};
+
+static const char * const mfg_sel_parents[] = {
+	"clk26m",
+	"mmpll",
+	"clk26m",
+	"clk26m",
+	"clk26m",
+	"clk26m",
+	"clk26m",
+	"clk26m",
+	"clk26m",
+	"syspll_d3",
+	"syspll1_d2",
+	"syspll_d5",
+	"univpll_d3",
+	"univpll1_d2"
+};
+
+static const char * const camtg_sel_parents[] = {
+	"clk26m",
+	"univpll_d26",
+	"univpll2_d2",
+	"syspll3_d2",
+	"syspll3_d4",
+	"msdcpll_d4"
+};
+
+static const char * const uart_sel_parents[] = {
+	"clk26m",
+	"univpll2_d8"
+};
+
+static const char * const spi_sel_parents[] = {
+	"clk26m",
+	"syspll3_d2",
+	"msdcpll_d8",
+	"syspll2_d4",
+	"syspll4_d2",
+	"univpll2_d4",
+	"univpll1_d8"
+};
+
+static const char * const usb20_sel_parents[] = {
+	"clk26m",
+	"univpll1_d8",
+	"univpll3_d4"
+};
+
+static const char * const msdc50_0_sel_parents[] = {
+	"clk26m",
+	"syspll1_d2",
+	"syspll2_d2",
+	"syspll4_d2",
+	"univpll_d5",
+	"univpll1_d4"
+};
+
+static const char * const msdc30_0_sel_parents[] = {
+	"clk26m",
+	"msdcpll",
+	"msdcpll_d2",
+	"msdcpll_d4",
+	"syspll2_d2",
+	"syspll1_d4",
+	"univpll1_d4",
+	"univpll_d3",
+	"univpll_d26",
+	"syspll2_d4",
+	"univpll_d2"
+};
+
+static const char * const msdc30_1_2_sel_parents[] = {
+	"clk26m",
+	"univpll2_d2",
+	"msdcpll_d4",
+	"syspll2_d2",
+	"syspll1_d4",
+	"univpll1_d4",
+	"univpll_d26",
+	"syspll2_d4"
+};
+
+static const char * const msdc30_3_sel_parents[] = {
+	"clk26m",
+	"univpll2_d2",
+	"msdcpll_d4",
+	"syspll2_d2",
+	"syspll1_d4",
+	"univpll1_d4",
+	"univpll_d26",
+	"msdcpll_d16",
+	"syspll2_d4"
+};
+
+static const char * const audio_sel_parents[] = {
+	"clk26m",
+	"syspll3_d4",
+	"syspll4_d4",
+	"syspll1_d16"
+};
+
+static const char * const aud_intbus_sel_parents[] = {
+	"clk26m",
+	"syspll1_d4",
+	"syspll4_d2",
+	"dmpll_d4"
+};
+
+static const char * const pmicspi_sel_parents[] = {
+	"clk26m",
+	"syspll1_d8",
+	"syspll3_d4",
+	"syspll1_d16",
+	"univpll3_d4",
+	"univpll_d26",
+	"dmpll_d4",
+	"dmpll_d8"
+};
+
+static const char * const scp_sel_parents[] = {
+	"clk26m",
+	"syspll1_d8",
+	"dmpll_d2",
+	"dmpll_d4"
+};
+
+static const char * const atb_sel_parents[] = {
+	"clk26m",
+	"syspll1_d2",
+	"syspll_d5",
+	"dmpll"
+};
+
+static const char * const dpi0_sel_parents[] = {
+	"clk26m",
+	"tvdpll",
+	"tvdpll_d2",
+	"tvdpll_d4",
+	"dpi_ck"
+};
+
+static const char * const scam_sel_parents[] = {
+	"clk26m",
+	"syspll3_d2",
+	"univpll2_d4",
+	"vencpll_d3"
+};
+
+static const char * const mfg13m_sel_parents[] = {
+	"clk26m",
+	"ad_sys_26m_d2"
+};
+
+static const char * const aud_1_2_sel_parents[] = {
+	"clk26m",
+	"apll1"
+};
+
+static const char * const irda_sel_parents[] = {
+	"clk26m",
+	"univpll2_d4"
+};
+
+static const char * const irtx_sel_parents[] = {
+	"clk26m",
+	"ad_sys_26m_ck"
+};
+
+static const char * const disppwm_sel_parents[] = {
+	"clk26m",
+	"univpll2_d4",
+	"syspll4_d2_d8",
+	"ad_sys_26m_ck"
+};
+
+static const struct mtk_mux topckgen_muxes[] = {
+	MUX_CLR_SET_UPD(AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
+	MUX_CLR_SET_UPD(MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
+	MUX_CLR_SET_UPD(DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0, 0),
+	MUX_GATE_CLR_SET_UPD(CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(UART_SEL, "uart_sel", uart_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 1, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(SPI_SEL, "spi_sel", spi_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, 0, 0),
+	MUX_GATE_CLR_SET_UPD(USB20_SEL, "usb20_sel", usb20_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 2, 23, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 4, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 3, 15, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 3, 23, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 4, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(AUDIO_SEL, "audio_sel", audio_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 2, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, 0, 0),
+	MUX_CLR_SET_UPD(PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 0, 0),
+	MUX_GATE_CLR_SET_UPD(SCP_SEL, "scp_sel", scp_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(ATB_SEL, "atb_sel", atb_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(DPI0_SEL, "dpi0_sel", dpi0_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, 0, 0),
+	MUX_GATE_CLR_SET_UPD(SCAM_SEL, "scam_sel", scam_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, 0, 0),
+	MUX_GATE_CLR_SET_UPD(MFG13M_SEL, "mfg13m_sel", mfg13m_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(AUD1_SEL, "aud_1_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 1, 7, 0, 0),
+	MUX_GATE_CLR_SET_UPD(AUD2_SEL, "aud_2_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 1, 15, 0, 0),
+	MUX_GATE_CLR_SET_UPD(IRDA_SEL, "irda_sel", irda_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 1, 23, 0, 0),
+	MUX_GATE_CLR_SET_UPD(IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 1, 31, 0, 0),
+	MUX_GATE_CLR_SET_UPD(DISPPWM_SEL, "disppwm_sel", disppwm_sel_parents, CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, 0, 0),
+};
+
+int clk_mt6735_topckgen_probe(struct platform_device *pdev)
+{
+	void __iomem *base;
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	struct clk_hw_onecell_data *clk_data;
+	int ret;
+
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(topckgen_fixed_clks) +
+				      ARRAY_SIZE(topckgen_factors) +
+				      ARRAY_SIZE(topckgen_muxes));
+	if (!clk_data)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, clk_data);
+
+	ret = mtk_clk_register_fixed_clks(topckgen_fixed_clks,
+					  ARRAY_SIZE(topckgen_fixed_clks),
+					  clk_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register fixed clocks: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = mtk_clk_register_factors(topckgen_factors, ARRAY_SIZE(topckgen_factors),
+				       clk_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register dividers: %d\n", ret);
+		return ret;
+	}
+
+	ret = mtk_clk_register_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
+				     pdev->dev.of_node, &mt6735_topckgen_lock,
+				     clk_data);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register muxes: %d\n", ret);
+		return ret;
+	}
+
+	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+					  clk_data);
+	if (ret)
+		dev_err(&pdev->dev,
+			"Failed to register clock provider: %d\n", ret);
+
+	return ret;
+}
+
+int clk_mt6735_topckgen_remove(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+	mtk_clk_unregister_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
+				 clk_data);
+	mtk_clk_unregister_factors(topckgen_factors, ARRAY_SIZE(topckgen_factors),
+				   clk_data);
+	mtk_clk_unregister_fixed_clks(topckgen_fixed_clks,
+				      ARRAY_SIZE(topckgen_fixed_clks),
+				      clk_data);
+	mtk_free_clk_data(clk_data);
+
+	return 0;
+}
+
+static const struct of_device_id of_match_mt6735_topckgen[] = {
+	{ .compatible = "mediatek,mt6735-topckgen", },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver clk_mt6735_topckgen = {
+	.probe = clk_mt6735_topckgen_probe,
+	.remove = clk_mt6735_topckgen_remove,
+	.driver = {
+		.name = "clk-mt6735-topckgen",
+		.of_match_table = of_match_mt6735_topckgen,
+	},
+};
+module_platform_driver(clk_mt6735_topckgen);
+
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("MediaTek MT6735 topckgen clock driver");
+MODULE_LICENSE("GPL");
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
@ 2023-02-25 12:05   ` kernel test robot
  2023-02-27  8:19   ` Krzysztof Kozlowski
  2023-02-27  9:28   ` AngeloGioacchino Del Regno
  2 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-02-25 12:05 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger,
	AngeloGioacchino Del Regno, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski
  Cc: oe-kbuild-all, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel

Hi Yassine,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master pza/reset/next v6.2 next-20230225]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yassine-Oudjana/dt-bindings-clock-Add-MediaTek-MT6735-clock-bindings/20230225-174603
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20230225094246.261697-5-y.oudjana%40protonmail.com
patch subject: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
config: sparc-allyesconfig (https://download.01.org/0day-ci/archive/20230225/202302251958.hFATZOVS-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/de4ed4bf78e894ade5d21d52861ee9e647d645a5
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Yassine-Oudjana/dt-bindings-clock-Add-MediaTek-MT6735-clock-bindings/20230225-174603
        git checkout de4ed4bf78e894ade5d21d52861ee9e647d645a5
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sparc olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sparc SHELL=/bin/bash drivers/clk/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302251958.hFATZOVS-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/mediatek/clk-mt6735-apmixedsys.c:80:5: warning: no previous prototype for 'clk_mt6735_apmixed_probe' [-Wmissing-prototypes]
      80 | int clk_mt6735_apmixed_probe(struct platform_device *pdev)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/clk/mediatek/clk-mt6735-apmixedsys.c:112:5: warning: no previous prototype for 'clk_mt6735_apmixed_remove' [-Wmissing-prototypes]
     112 | int clk_mt6735_apmixed_remove(struct platform_device *pdev)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~
--
>> drivers/clk/mediatek/clk-mt6735-topckgen.c:366:5: warning: no previous prototype for 'clk_mt6735_topckgen_probe' [-Wmissing-prototypes]
     366 | int clk_mt6735_topckgen_probe(struct platform_device *pdev)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/mediatek/clk-mt6735-topckgen.c: In function 'clk_mt6735_topckgen_probe':
   drivers/clk/mediatek/clk-mt6735-topckgen.c:400:38: error: passing argument 1 of 'mtk_clk_register_muxes' from incompatible pointer type [-Werror=incompatible-pointer-types]
     400 |         ret = mtk_clk_register_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
         |                                      ^~~~~~~~~~~~~~
         |                                      |
         |                                      const struct mtk_mux *
   In file included from drivers/clk/mediatek/clk-mt6735-topckgen.c:10:
   drivers/clk/mediatek/clk-mux.h:86:43: note: expected 'struct device *' but argument is of type 'const struct mtk_mux *'
      86 | int mtk_clk_register_muxes(struct device *dev,
         |                            ~~~~~~~~~~~~~~~^~~
   In file included from include/linux/cpumask.h:10,
                    from include/linux/smp.h:13,
                    from include/linux/lockdep.h:14,
                    from include/linux/mutex.h:17,
                    from include/linux/kernfs.h:11,
                    from include/linux/sysfs.h:16,
                    from include/linux/kobject.h:20,
                    from include/linux/of.h:17,
                    from include/linux/clk-provider.h:9,
                    from drivers/clk/mediatek/clk-mt6735-topckgen.c:6:
>> include/linux/kernel.h:55:25: warning: passing argument 2 of 'mtk_clk_register_muxes' makes pointer from integer without a cast [-Wint-conversion]
      55 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
         |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
         |                         |
         |                         long unsigned int
   drivers/clk/mediatek/clk-mt6735-topckgen.c:400:54: note: in expansion of macro 'ARRAY_SIZE'
     400 |         ret = mtk_clk_register_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
         |                                                      ^~~~~~~~~~
   drivers/clk/mediatek/clk-mux.h:87:50: note: expected 'const struct mtk_mux *' but argument is of type 'long unsigned int'
      87 |                            const struct mtk_mux *muxes,
         |                            ~~~~~~~~~~~~~~~~~~~~~~^~~~~
>> drivers/clk/mediatek/clk-mt6735-topckgen.c:401:47: warning: passing argument 3 of 'mtk_clk_register_muxes' makes integer from pointer without a cast [-Wint-conversion]
     401 |                                      pdev->dev.of_node, &mt6735_topckgen_lock,
         |                                      ~~~~~~~~~^~~~~~~~
         |                                               |
         |                                               struct device_node *
   drivers/clk/mediatek/clk-mux.h:88:32: note: expected 'int' but argument is of type 'struct device_node *'
      88 |                            int num, struct device_node *node,
         |                            ~~~~^~~
   drivers/clk/mediatek/clk-mt6735-topckgen.c:401:57: error: passing argument 4 of 'mtk_clk_register_muxes' from incompatible pointer type [-Werror=incompatible-pointer-types]
     401 |                                      pdev->dev.of_node, &mt6735_topckgen_lock,
         |                                                         ^~~~~~~~~~~~~~~~~~~~~
         |                                                         |
         |                                                         spinlock_t * {aka struct spinlock *}
   drivers/clk/mediatek/clk-mux.h:88:57: note: expected 'struct device_node *' but argument is of type 'spinlock_t *' {aka 'struct spinlock *'}
      88 |                            int num, struct device_node *node,
         |                                     ~~~~~~~~~~~~~~~~~~~~^~~~
   drivers/clk/mediatek/clk-mt6735-topckgen.c:402:38: error: passing argument 5 of 'mtk_clk_register_muxes' from incompatible pointer type [-Werror=incompatible-pointer-types]
     402 |                                      clk_data);
         |                                      ^~~~~~~~
         |                                      |
         |                                      struct clk_hw_onecell_data *
   drivers/clk/mediatek/clk-mux.h:89:40: note: expected 'spinlock_t *' {aka 'struct spinlock *'} but argument is of type 'struct clk_hw_onecell_data *'
      89 |                            spinlock_t *lock,
         |                            ~~~~~~~~~~~~^~~~
   drivers/clk/mediatek/clk-mt6735-topckgen.c:400:15: error: too few arguments to function 'mtk_clk_register_muxes'
     400 |         ret = mtk_clk_register_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
         |               ^~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/mediatek/clk-mux.h:86:5: note: declared here
      86 | int mtk_clk_register_muxes(struct device *dev,
         |     ^~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/mediatek/clk-mt6735-topckgen.c: At top level:
>> drivers/clk/mediatek/clk-mt6735-topckgen.c:417:5: warning: no previous prototype for 'clk_mt6735_topckgen_remove' [-Wmissing-prototypes]
     417 | int clk_mt6735_topckgen_remove(struct platform_device *pdev)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/clk_mt6735_apmixed_probe +80 drivers/clk/mediatek/clk-mt6735-apmixedsys.c

    79	
  > 80	int clk_mt6735_apmixed_probe(struct platform_device *pdev)
    81	{
    82		void __iomem *base;
    83		struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    84		struct clk_hw_onecell_data *clk_data;
    85		int ret;
    86	
    87		base = devm_ioremap_resource(&pdev->dev, res);
    88		if (IS_ERR(base))
    89			return PTR_ERR(base);
    90	
    91		clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixedsys_plls));
    92		if (!clk_data)
    93			return -ENOMEM;
    94		platform_set_drvdata(pdev, clk_data);
    95	
    96		ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
    97					   ARRAY_SIZE(apmixedsys_plls), clk_data);
    98		if (ret) {
    99			dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
   100			return ret;
   101		}
   102	
   103		ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
   104						  clk_data);
   105		if (ret)
   106			dev_err(&pdev->dev,
   107				"Failed to register clock provider: %d\n", ret);
   108	
   109		return ret;
   110	}
   111	
 > 112	int clk_mt6735_apmixed_remove(struct platform_device *pdev)
   113	{
   114		struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
   115	
   116		mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
   117		mtk_free_clk_data(clk_data);
   118	
   119		return 0;
   120	}
   121	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings
  2023-02-25  9:42 ` [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings Yassine Oudjana
@ 2023-02-27  8:17   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-27  8:17 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger,
	AngeloGioacchino Del Regno, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski
  Cc: Yassine Oudjana, devicetree, linux-kernel, linux-clk,
	linux-mediatek, linux-arm-kernel, Rob Herring

On 25/02/2023 10:42, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add reset definitions for the main reset controllers of MT6735 (infracfg
> and pericfg).
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  MAINTAINERS                                   |  4 ++-
>  .../reset/mediatek,mt6735-infracfg.h          | 31 +++++++++++++++++++
>  .../reset/mediatek,mt6735-pericfg.h           | 31 +++++++++++++++++++
>  3 files changed, 65 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
>  create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5323f71c48fb..f617042790ee 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13101,7 +13101,7 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>  F:	drivers/mmc/host/mtk-sd.c
>  
> -MEDIATEK MT6735 CLOCK DRIVERS
> +MEDIATEK MT6735 CLOCK & RESET DRIVERS

You just added this line in previous patch. Don't add code which
immediately you fix.



Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
  2023-02-25  9:42 ` [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
@ 2023-02-27  8:18   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-27  8:18 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger,
	AngeloGioacchino Del Regno, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski
  Cc: Yassine Oudjana, devicetree, linux-kernel, linux-clk,
	linux-mediatek, linux-arm-kernel, Rob Herring

On 25/02/2023 10:42, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add compatible strings for MT6735 apmixedsys, topckgen, infracfg
> and pericfg.
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  .../bindings/arm/mediatek/mediatek,infracfg.yaml          | 8 +++++---
>  .../bindings/arm/mediatek/mediatek,pericfg.yaml           | 1 +
>  .../devicetree/bindings/clock/mediatek,apmixedsys.yaml    | 4 +++-
>  .../devicetree/bindings/clock/mediatek,topckgen.yaml      | 4 +++-
>  4 files changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> index e997635e4fe4..715e24a4ddda 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

All the previous patches should be squashed here. There is no reason to
split adding new binding for clock into two separate patches. It is
still one new binding for clock.



Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings
  2023-02-25  9:42 ` [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings Yassine Oudjana
@ 2023-02-27  8:18   ` Krzysztof Kozlowski
  2023-02-27  8:29     ` Yassine Oudjana
  0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-27  8:18 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger,
	AngeloGioacchino Del Regno, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski
  Cc: Yassine Oudjana, devicetree, linux-kernel, linux-clk,
	linux-mediatek, linux-arm-kernel, Rob Herring

On 25/02/2023 10:42, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add clock definitions for the main clock controllers of MT6735 (apmixedsys,
> topckgen, infracfg and pericfg).
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  MAINTAINERS                                   | 10 +++
>  .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>  .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>  .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>  .../clock/mediatek,mt6735-topckgen.h          | 79 +++++++++++++++++++
>  5 files changed, 167 insertions(+)

You should squash it with other part of binding. What is the reason
behind splitting one binding into three patches?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  2023-02-25 12:05   ` kernel test robot
@ 2023-02-27  8:19   ` Krzysztof Kozlowski
  2023-02-27  9:28   ` AngeloGioacchino Del Regno
  2 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-27  8:19 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger,
	AngeloGioacchino Del Regno, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski
  Cc: Yassine Oudjana, devicetree, linux-kernel, linux-clk,
	linux-mediatek, linux-arm-kernel

On 25/02/2023 10:42, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
> clock and reset controllers. These provide the base clocks and resets
> on the platform, and should be enough to bring up all essential blocks
> including PWRAP, MSDC and peripherals (UART, I2C, SPI).
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
>  MAINTAINERS                                  |   4 +
>  drivers/clk/mediatek/Kconfig                 |   9 +
>  drivers/clk/mediatek/Makefile                |   1 +
>  drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++
>  drivers/clk/mediatek/clk-mt6735-infracfg.c   |  78 ++++
>  drivers/clk/mediatek/clk-mt6735-pericfg.c    |  91 ++++
>  drivers/clk/mediatek/clk-mt6735-topckgen.c   | 450 +++++++++++++++++++
>  7 files changed, 772 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f617042790ee..d7ec4a36a934 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13106,6 +13106,10 @@ M:	Yassine Oudjana <y.oudjana@protonmail.com>
>  L:	linux-clk@vger.kernel.org
>  L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
> +F:	drivers/clk/mediatek/clk-mt6735-apmixedsys.c
> +F:	drivers/clk/mediatek/clk-mt6735-infracfg.c
> +F:	drivers/clk/mediatek/clk-mt6735-pericfg.c
> +F:	drivers/clk/mediatek/clk-mt6735-topckgen.c
>  F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
>  F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h
>  F:	include/dt-bindings/clock/mediatek,mt6735-pericfg.h
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 2d14855dd37e..593791c0a7d6 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -124,6 +124,15 @@ config COMMON_CLK_MT2712_VENCSYS
>  	help
>  	  This driver supports MediaTek MT2712 vencsys clocks.
>  
> +config COMMON_CLK_MT6735
> +	tristate "Main clock drivers for MediaTek MT6735"
> +	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	select COMMON_CLK_MEDIATEK
> +	help
> +	  This enables drivers for clocks and resets provided
> +	  by apmixedsys, topckgen, infracfg and pericfg on the
> +	  MediaTek MT6735 SoC.
> +
>  config COMMON_CLK_MT6765
>         bool "Clock driver for MediaTek MT6765"
>         depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index e5d018270ed0..d2496a8d0467 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -2,6 +2,7 @@
>  obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
>  obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
>  
> +obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
>  obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
>  obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
>  obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
> new file mode 100644
> index 000000000000..5ce395c34d92
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c
> @@ -0,0 +1,139 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-pll.h"
> +
> +#include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
> +
> +#define AP_PLL_CON_5		0x014
> +#define ARMPLL_CON0		0x200
> +#define ARMPLL_CON1		0x204
> +#define ARMPLL_PWR_CON0		0x20c
> +#define MAINPLL_CON0		0x210
> +#define MAINPLL_CON1		0x214
> +#define MAINPLL_PWR_CON0	0x21c
> +#define UNIVPLL_CON0		0x220
> +#define UNIVPLL_CON1		0x224
> +#define UNIVPLL_PWR_CON0	0x22c
> +#define MMPLL_CON0		0x230
> +#define MMPLL_CON1		0x234
> +#define MMPLL_PWR_CON0		0x23c
> +#define MSDCPLL_CON0		0x240
> +#define MSDCPLL_CON1		0x244
> +#define MSDCPLL_PWR_CON0	0x24c
> +#define VENCPLL_CON0		0x250
> +#define VENCPLL_CON1		0x254
> +#define VENCPLL_PWR_CON0	0x25c
> +#define TVDPLL_CON0		0x260
> +#define TVDPLL_CON1		0x264
> +#define TVDPLL_PWR_CON0		0x26c
> +#define APLL1_CON0		0x270
> +#define APLL1_CON1		0x274
> +#define APLL1_CON2		0x278
> +#define APLL1_PWR_CON0		0x280
> +#define APLL2_CON0		0x284
> +#define APLL2_CON1		0x288
> +#define APLL2_CON2		0x28c
> +#define APLL2_PWR_CON0		0x294
> +
> +#define CON0_RST_BAR		BIT(24)
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask,	\
> +	    _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,		\
> +	    _tuner_en_bit, _pcw_reg, _pcwbits, _flags) {		\
> +		.id = _id,						\
> +		.name = _name,						\
> +		.parent_name = "clk26m",				\
> +		.reg = _reg,						\
> +		.pwr_reg = _pwr_reg,					\
> +		.en_mask = _en_mask,					\
> +		.rst_bar_mask = _rst_bar_mask,				\
> +		.pd_reg = _pd_reg,					\
> +		.pd_shift = _pd_shift,					\
> +		.tuner_reg = _tuner_reg,				\
> +		.tuner_en_reg = _tuner_en_reg,				\
> +		.tuner_en_bit = _tuner_en_bit,				\
> +		.pcw_reg = _pcw_reg,					\
> +		.pcw_chg_reg = _pcw_reg,				\
> +		.pcwbits = _pcwbits,					\
> +		.flags = _flags,					\
> +	}
> +
> +static const struct mtk_pll_data apmixedsys_plls[] = {
> +	PLL(ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO),
> +	PLL(MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_RST_BAR),
> +	PLL(UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_RST_BAR),
> +	PLL(MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
> +	PLL(MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 24, 0, 0, 0, MSDCPLL_CON1, 21, 0),
> +	PLL(VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENCPLL_CON1, 24, 0, 0, 0, VENCPLL_CON1, 21, HAVE_RST_BAR),
> +	PLL(TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0, 0, 0, TVDPLL_CON1, 21, 0),
> +	PLL(APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CON2, AP_PLL_CON_5, 0, APLL1_CON1, 31, 0),
> +	PLL(APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
> +};
> +
> +int clk_mt6735_apmixed_probe(struct platform_device *pdev)
> +{
> +	void __iomem *base;
> +	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	struct clk_hw_onecell_data *clk_data;
> +	int ret;
> +
> +	base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixedsys_plls));
> +	if (!clk_data)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, clk_data);
> +
> +	ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
> +				   ARRAY_SIZE(apmixedsys_plls), clk_data);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> +					  clk_data);
> +	if (ret)
> +		dev_err(&pdev->dev,
> +			"Failed to register clock provider: %d\n", ret);
> +
> +	return ret;
> +}
> +
> +int clk_mt6735_apmixed_remove(struct platform_device *pdev)
> +{
> +	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> +	mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
> +	mtk_free_clk_data(clk_data);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id of_match_mt6735_apmixedsys[] = {
> +	{ .compatible = "mediatek,mt6735-apmixedsys" },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt6735_apmixedsys = {
> +	.probe = clk_mt6735_apmixed_probe,
> +	.remove = clk_mt6735_apmixed_remove,
> +	.driver = {
> +		.name = "clk-mt6735-apmixedsys",
> +		.of_match_table = of_match_mt6735_apmixedsys,
> +	},
> +};
> +module_platform_driver(clk_mt6735_apmixedsys);
> +
> +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
> +MODULE_DESCRIPTION("MediaTek MT6735 apmixedsys clock driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/mediatek/clk-mt6735-infracfg.c
> new file mode 100644
> index 000000000000..e9dd3caa5f97
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c
> @@ -0,0 +1,78 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
> +
> +#define INFRA_RST0			0x30
> +#define INFRA_GLOBALCON_PDN0		0x40
> +#define INFRA_PDN1			0x44
> +#define	INFRA_PDN_STA			0x48
> +
> +static struct mtk_gate_regs infra_cg_regs = {
> +	.set_ofs = INFRA_GLOBALCON_PDN0,
> +	.clr_ofs = INFRA_PDN1,
> +	.sta_ofs = INFRA_PDN_STA,
> +};
> +
> +static const struct mtk_gate infracfg_gates[] = {
> +	GATE_MTK(CLK_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK_FLAGS(CLK_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
> +	GATE_MTK(CLK_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
> +};
> +
> +static u16 infracfg_rst_ofs[] = { INFRA_RST0 };
> +
> +static const struct mtk_clk_rst_desc infracfg_resets = {
> +	.version = MTK_RST_SIMPLE,
> +	.rst_bank_ofs = infracfg_rst_ofs,
> +	.rst_bank_nr = ARRAY_SIZE(infracfg_rst_ofs)
> +};
> +
> +static const struct mtk_clk_desc infracfg_clks = {
> +	.clks = infracfg_gates,
> +	.num_clks = ARRAY_SIZE(infracfg_gates),
> +
> +	.rst_desc = &infracfg_resets
> +};
> +
> +static const struct of_device_id of_match_mt6735_infracfg[] = {
> +	{ .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt6735_infracfg = {
> +	.probe = mtk_clk_simple_probe,
> +	.remove = mtk_clk_simple_remove,
> +	.driver = {
> +		.name = "clk-mt6735-infracfg",
> +		.of_match_table = of_match_mt6735_infracfg,
> +	},
> +};
> +module_platform_driver(clk_mt6735_infracfg);
> +
> +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
> +MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediatek/clk-mt6735-pericfg.c
> new file mode 100644
> index 000000000000..4d74e345509b
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mediatek,mt6735-pericfg.h>
> +
> +#define PERI_GLOBALCON_RST0		0x00
> +#define PERI_GLOBALCON_RST1		0x04
> +#define PERI_GLOBALCON_PDN0_SET		0x08
> +#define PERI_GLOBALCON_PDN0_CLR		0x10
> +#define	PERI_GLOBALCON_PDN0_STA		0x18
> +
> +static struct mtk_gate_regs peri_cg_regs = {
> +	.set_ofs = PERI_GLOBALCON_PDN0_SET,
> +	.clr_ofs = PERI_GLOBALCON_PDN0_CLR,
> +	.sta_ofs = PERI_GLOBALCON_PDN0_STA,
> +};
> +
> +static const struct mtk_gate pericfg_gates[] = {
> +	GATE_MTK(CLK_DISP_PWM, "disp_pwm", "disppwm_sel", &peri_cg_regs, 0, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_THERM, "therm", "axi_sel", &peri_cg_regs, 1, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_PWM, "pwm", "axi_sel", &peri_cg_regs, 9, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_USB0, "usb0", "usb20_sel", &peri_cg_regs, 10, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_IRDA, "irda", "irda_sel", &peri_cg_regs, 11, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_APDMA, "apdma", "axi_sel", &peri_cg_regs, 12, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_MSDC30_0, "msdc30_0", "msdc30_0_sel", &peri_cg_regs, 13, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_MSDC30_1, "msdc30_1", "msdc30_1_sel", &peri_cg_regs, 14, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_MSDC30_2, "msdc30_2", "msdc30_2_sel", &peri_cg_regs, 15, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_MSDC30_3, "msdc30_3", "msdc30_3_sel", &peri_cg_regs, 16, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_UART1, "uart1", "uart_sel", &peri_cg_regs, 18, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_UART3, "uart3", "uart_sel", &peri_cg_regs, 20, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_UART4, "uart4", "uart_sel", &peri_cg_regs, 21, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_BTIF, "btif", "axi_sel", &peri_cg_regs, 22, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_I2C0, "i2c0", "axi_sel", &peri_cg_regs, 23, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_I2C1, "i2c1", "axi_sel", &peri_cg_regs, 24, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_I2C2, "i2c2", "axi_sel", &peri_cg_regs, 25, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_I2C3, "i2c3", "axi_sel", &peri_cg_regs, 26, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_AUXADC, "auxadc", "axi_sel", &peri_cg_regs, 27, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_SPI0, "spi0", "spi_sel", &peri_cg_regs, 28, &mtk_clk_gate_ops_setclr),
> +	GATE_MTK(CLK_IRTX, "irtx", "irtx_sel", &peri_cg_regs, 29, &mtk_clk_gate_ops_setclr)
> +};
> +
> +static u16 pericfg_rst_ofs[] = { PERI_GLOBALCON_RST0, PERI_GLOBALCON_RST1 };
> +
> +static const struct mtk_clk_rst_desc pericfg_resets = {
> +	.version = MTK_RST_SIMPLE,
> +	.rst_bank_ofs = pericfg_rst_ofs,
> +	.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs)
> +};
> +
> +static const struct mtk_clk_desc pericfg_clks = {
> +	.clks = pericfg_gates,
> +	.num_clks = ARRAY_SIZE(pericfg_gates),
> +
> +	.rst_desc = &pericfg_resets
> +};
> +
> +static const struct of_device_id of_match_mt6735_pericfg[] = {
> +	{ .compatible = "mediatek,mt6735-pericfg", .data = &pericfg_clks },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt6735_pericfg = {
> +	.probe = mtk_clk_simple_probe,
> +	.remove = mtk_clk_simple_remove,
> +	.driver = {
> +		.name = "clk-mt6735-pericfg",
> +		.of_match_table = of_match_mt6735_pericfg,
> +	},
> +};
> +module_platform_driver(clk_mt6735_pericfg);
> +
> +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
> +MODULE_DESCRIPTION("MediaTek MT6735 pericfg clock driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/mediatek/clk-mt6735-topckgen.c
> new file mode 100644
> index 000000000000..5fa743e4b0fc
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c
> @@ -0,0 +1,450 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
> +
> +#define CLK_CFG_0		0x40
> +#define CLK_CFG_0_SET		0x44
> +#define CLK_CFG_0_CLR		0x48
> +#define CLK_CFG_1		0x50
> +#define CLK_CFG_1_SET		0x54
> +#define CLK_CFG_1_CLR		0x58
> +#define CLK_CFG_2		0x60
> +#define CLK_CFG_2_SET		0x64
> +#define CLK_CFG_2_CLR		0x68
> +#define CLK_CFG_3		0x70
> +#define CLK_CFG_3_SET		0x74
> +#define CLK_CFG_3_CLR		0x78
> +#define CLK_CFG_4		0x80
> +#define CLK_CFG_4_SET		0x84
> +#define CLK_CFG_4_CLR		0x88
> +#define CLK_CFG_5		0x90
> +#define CLK_CFG_5_SET		0x94
> +#define CLK_CFG_5_CLR		0x98
> +#define CLK_CFG_6		0xa0
> +#define CLK_CFG_6_SET		0xa4
> +#define CLK_CFG_6_CLR		0xa8
> +#define CLK_CFG_7		0xb0
> +#define CLK_CFG_7_SET		0xb4
> +#define CLK_CFG_7_CLR		0xb8
> +
> +static DEFINE_SPINLOCK(mt6735_topckgen_lock);
> +
> +/* Some clocks with unknown details are modeled as fixed clocks */
> +static const struct mtk_fixed_clk topckgen_fixed_clks[] = {
> +	/*
> +	 * This clock is available as a parent option for multiple
> +	 * muxes and seems like an alternative name for clk26m at first,
> +	 * but it appears alongside it in several muxes which should
> +	 * mean it is a separate clock.
> +	 */
> +	FIXED_CLK(AD_SYS_26M_CK, "ad_sys_26m_ck", "clk26m", 26 * MHZ),
> +	/*
> +	 * This clock is the parent of DMPLL divisors. It might be MEMPLL
> +	 * or its parent, as DMPLL appears to be an alternative name for
> +	 * MEMPLL.
> +	 */
> +	FIXED_CLK(CLKPH_MCK_O, "clkph_mck_o", NULL, 0),
> +	/*
> +	 * DMPLL clock (dmpll_ck), controlled by DDRPHY.
> +	 */
> +	FIXED_CLK(DMPLL, "dmpll", "clkph_mck_o", 0),
> +	/*
> +	 * MIPI DPI clock. Parent option for dpi0_sel. Unknown parent.
> +	 */
> +	FIXED_CLK(DPI_CK, "dpi_ck", NULL, 0),
> +	/*
> +	 * This clock is a child of WHPLL which is controlled by
> +	 * the modem.
> +	 */
> +	FIXED_CLK(WHPLL_AUDIO_CK, "whpll_audio_ck", NULL, 0)
> +};
> +
> +static const struct mtk_fixed_factor topckgen_factors[] = {
> +	FACTOR(SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
> +	FACTOR(SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
> +	FACTOR(SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
> +	FACTOR(SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 2),
> +	FACTOR(SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 4),
> +	FACTOR(SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 8),
> +	FACTOR(SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 16),
> +	FACTOR(SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 2),
> +	FACTOR(SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 4),
> +	FACTOR(SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 2),
> +	FACTOR(SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 4),
> +	FACTOR(SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 2),
> +	FACTOR(SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 4),
> +	FACTOR(UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
> +	FACTOR(UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
> +	FACTOR(UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
> +	FACTOR(UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
> +	FACTOR(UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 2),
> +	FACTOR(UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 4),
> +	FACTOR(UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 8),
> +	FACTOR(UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
> +	FACTOR(UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
> +	FACTOR(UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
> +	FACTOR(UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 2),
> +	FACTOR(UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 4),
> +	FACTOR(MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
> +	FACTOR(MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
> +	FACTOR(MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
> +	FACTOR(MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
> +	FACTOR(VENCPLL_D3, "vencpll_d3", "vencpll", 1, 3),
> +	FACTOR(TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
> +	FACTOR(TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
> +	FACTOR(DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
> +	FACTOR(DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
> +	FACTOR(DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
> +	FACTOR(AD_SYS_26M_D2, "ad_sys_26m_d2", "clk26m", 1, 2)
> +};
> +
> +static const char * const axi_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d2",
> +	"syspll_d5",
> +	"syspll1_d4",
> +	"univpll_d5",
> +	"univpll2_d2",
> +	"dmpll",
> +	"dmpll_d2"
> +};
> +
> +static const char * const mem_sel_parents[] = {
> +	"clk26m",
> +	"dmpll"
> +};
> +
> +static const char * const ddrphycfg_parents[] = {
> +	"clk26m",
> +	"syspll1_d8"
> +};
> +
> +static const char * const mm_sel_parents[] = {
> +	"clk26m",
> +	"vencpll",
> +	"syspll1_d2",
> +	"syspll_d5",
> +	"syspll1_d4",
> +	"univpll_d5",
> +	"univpll2_d2",
> +	"dmpll"
> +};
> +
> +static const char * const pwm_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d4",
> +	"univpll3_d2",
> +	"univpll1_d4"
> +};
> +
> +static const char * const vdec_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d2",
> +	"syspll_d5",
> +	"syspll1_d4",
> +	"univpll_d5",
> +	"syspll_d2",
> +	"syspll2_d2",
> +	"msdcpll_d2"
> +};
> +
> +static const char * const mfg_sel_parents[] = {
> +	"clk26m",
> +	"mmpll",
> +	"clk26m",
> +	"clk26m",
> +	"clk26m",
> +	"clk26m",
> +	"clk26m",
> +	"clk26m",
> +	"clk26m",
> +	"syspll_d3",
> +	"syspll1_d2",
> +	"syspll_d5",
> +	"univpll_d3",
> +	"univpll1_d2"
> +};
> +
> +static const char * const camtg_sel_parents[] = {
> +	"clk26m",
> +	"univpll_d26",
> +	"univpll2_d2",
> +	"syspll3_d2",
> +	"syspll3_d4",
> +	"msdcpll_d4"
> +};
> +
> +static const char * const uart_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d8"
> +};
> +
> +static const char * const spi_sel_parents[] = {
> +	"clk26m",
> +	"syspll3_d2",
> +	"msdcpll_d8",
> +	"syspll2_d4",
> +	"syspll4_d2",
> +	"univpll2_d4",
> +	"univpll1_d8"
> +};
> +
> +static const char * const usb20_sel_parents[] = {
> +	"clk26m",
> +	"univpll1_d8",
> +	"univpll3_d4"
> +};
> +
> +static const char * const msdc50_0_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d2",
> +	"syspll2_d2",
> +	"syspll4_d2",
> +	"univpll_d5",
> +	"univpll1_d4"
> +};
> +
> +static const char * const msdc30_0_sel_parents[] = {
> +	"clk26m",
> +	"msdcpll",
> +	"msdcpll_d2",
> +	"msdcpll_d4",
> +	"syspll2_d2",
> +	"syspll1_d4",
> +	"univpll1_d4",
> +	"univpll_d3",
> +	"univpll_d26",
> +	"syspll2_d4",
> +	"univpll_d2"
> +};
> +
> +static const char * const msdc30_1_2_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d2",
> +	"msdcpll_d4",
> +	"syspll2_d2",
> +	"syspll1_d4",
> +	"univpll1_d4",
> +	"univpll_d26",
> +	"syspll2_d4"
> +};
> +
> +static const char * const msdc30_3_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d2",
> +	"msdcpll_d4",
> +	"syspll2_d2",
> +	"syspll1_d4",
> +	"univpll1_d4",
> +	"univpll_d26",
> +	"msdcpll_d16",
> +	"syspll2_d4"
> +};
> +
> +static const char * const audio_sel_parents[] = {
> +	"clk26m",
> +	"syspll3_d4",
> +	"syspll4_d4",
> +	"syspll1_d16"
> +};
> +
> +static const char * const aud_intbus_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d4",
> +	"syspll4_d2",
> +	"dmpll_d4"
> +};
> +
> +static const char * const pmicspi_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d8",
> +	"syspll3_d4",
> +	"syspll1_d16",
> +	"univpll3_d4",
> +	"univpll_d26",
> +	"dmpll_d4",
> +	"dmpll_d8"
> +};
> +
> +static const char * const scp_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d8",
> +	"dmpll_d2",
> +	"dmpll_d4"
> +};
> +
> +static const char * const atb_sel_parents[] = {
> +	"clk26m",
> +	"syspll1_d2",
> +	"syspll_d5",
> +	"dmpll"
> +};
> +
> +static const char * const dpi0_sel_parents[] = {
> +	"clk26m",
> +	"tvdpll",
> +	"tvdpll_d2",
> +	"tvdpll_d4",
> +	"dpi_ck"
> +};
> +
> +static const char * const scam_sel_parents[] = {
> +	"clk26m",
> +	"syspll3_d2",
> +	"univpll2_d4",
> +	"vencpll_d3"
> +};
> +
> +static const char * const mfg13m_sel_parents[] = {
> +	"clk26m",
> +	"ad_sys_26m_d2"
> +};
> +
> +static const char * const aud_1_2_sel_parents[] = {
> +	"clk26m",
> +	"apll1"
> +};
> +
> +static const char * const irda_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d4"
> +};
> +
> +static const char * const irtx_sel_parents[] = {
> +	"clk26m",
> +	"ad_sys_26m_ck"
> +};
> +
> +static const char * const disppwm_sel_parents[] = {
> +	"clk26m",
> +	"univpll2_d4",
> +	"syspll4_d2_d8",
> +	"ad_sys_26m_ck"
> +};
> +
> +static const struct mtk_mux topckgen_muxes[] = {
> +	MUX_CLR_SET_UPD(AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
> +	MUX_CLR_SET_UPD(MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
> +	MUX_CLR_SET_UPD(DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(UART_SEL, "uart_sel", uart_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 1, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(SPI_SEL, "spi_sel", spi_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(USB20_SEL, "usb20_sel", usb20_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 2, 23, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 4, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 3, 15, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 3, 23, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 4, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(AUDIO_SEL, "audio_sel", audio_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 2, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, 0, 0),
> +	MUX_CLR_SET_UPD(PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(SCP_SEL, "scp_sel", scp_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(ATB_SEL, "atb_sel", atb_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(DPI0_SEL, "dpi0_sel", dpi0_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(SCAM_SEL, "scam_sel", scam_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(MFG13M_SEL, "mfg13m_sel", mfg13m_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(AUD1_SEL, "aud_1_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 1, 7, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(AUD2_SEL, "aud_2_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 1, 15, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(IRDA_SEL, "irda_sel", irda_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 1, 23, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 1, 31, 0, 0),
> +	MUX_GATE_CLR_SET_UPD(DISPPWM_SEL, "disppwm_sel", disppwm_sel_parents, CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, 0, 0),
> +};
> +
> +int clk_mt6735_topckgen_probe(struct platform_device *pdev)
> +{
> +	void __iomem *base;
> +	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	struct clk_hw_onecell_data *clk_data;
> +	int ret;
> +
> +	base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(topckgen_fixed_clks) +
> +				      ARRAY_SIZE(topckgen_factors) +
> +				      ARRAY_SIZE(topckgen_muxes));
> +	if (!clk_data)
> +		return -ENOMEM;
> +	platform_set_drvdata(pdev, clk_data);
> +
> +	ret = mtk_clk_register_fixed_clks(topckgen_fixed_clks,
> +					  ARRAY_SIZE(topckgen_fixed_clks),
> +					  clk_data);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register fixed clocks: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	ret = mtk_clk_register_factors(topckgen_factors, ARRAY_SIZE(topckgen_factors),
> +				       clk_data);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register dividers: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = mtk_clk_register_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
> +				     pdev->dev.of_node, &mt6735_topckgen_lock,
> +				     clk_data);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to register muxes: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> +					  clk_data);
> +	if (ret)
> +		dev_err(&pdev->dev,
> +			"Failed to register clock provider: %d\n", ret);
> +
> +	return ret;
> +}
> +
> +int clk_mt6735_topckgen_remove(struct platform_device *pdev)
> +{
> +	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> +	mtk_clk_unregister_muxes(topckgen_muxes, ARRAY_SIZE(topckgen_muxes),
> +				 clk_data);
> +	mtk_clk_unregister_factors(topckgen_factors, ARRAY_SIZE(topckgen_factors),
> +				   clk_data);
> +	mtk_clk_unregister_fixed_clks(topckgen_fixed_clks,
> +				      ARRAY_SIZE(topckgen_fixed_clks),
> +				      clk_data);
> +	mtk_free_clk_data(clk_data);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id of_match_mt6735_topckgen[] = {
> +	{ .compatible = "mediatek,mt6735-topckgen", },
> +	{ /* sentinel */ }
> +};

Missing module device table. Maybe in other pieces as well.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings
  2023-02-27  8:18   ` Krzysztof Kozlowski
@ 2023-02-27  8:29     ` Yassine Oudjana
  2023-02-27  9:08       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-27  8:29 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski, Yassine Oudjana,
	devicetree, linux-kernel, linux-clk, linux-mediatek,
	linux-arm-kernel, Rob Herring


On Mon, Feb 27 2023 at 09:18:45 AM +01:00:00, Krzysztof Kozlowski 
<krzysztof.kozlowski@linaro.org> wrote:
> On 25/02/2023 10:42, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Add clock definitions for the main clock controllers of MT6735 
>> (apmixedsys,
>>  topckgen, infracfg and pericfg).
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  Acked-by: Rob Herring <robh@kernel.org>
>>  ---
>>   MAINTAINERS                                   | 10 +++
>>   .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>>   .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>>   .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>>   .../clock/mediatek,mt6735-topckgen.h          | 79 
>> +++++++++++++++++++
>>   5 files changed, 167 insertions(+)
> 
> You should squash it with other part of binding. What is the reason
> behind splitting one binding into three patches?

It seemed logical to me that each of clock and reset bindings as well 
as documentation would be separate parts especially since they go in 
different paths, but if combining them is how it's done then sure, I'll 
squash them and resend.




^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings
  2023-02-27  8:29     ` Yassine Oudjana
@ 2023-02-27  9:08       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-27  9:08 UTC (permalink / raw)
  To: Yassine Oudjana
  Cc: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
	Philipp Zabel, Daniel Golle, Allen-KH Cheng, Tinghan Shen,
	Chen-Yu Tsai, Edward-JW Yang, Johnson Wang, Fabien Parent,
	Chun-Jie Chen, Miles Chen, Bartosz Golaszewski, Yassine Oudjana,
	devicetree, linux-kernel, linux-clk, linux-mediatek,
	linux-arm-kernel, Rob Herring

On 27/02/2023 09:29, Yassine Oudjana wrote:
> 
> On Mon, Feb 27 2023 at 09:18:45 AM +01:00:00, Krzysztof Kozlowski 
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 25/02/2023 10:42, Yassine Oudjana wrote:
>>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>>>
>>>  Add clock definitions for the main clock controllers of MT6735 
>>> (apmixedsys,
>>>  topckgen, infracfg and pericfg).
>>>
>>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>>  Acked-by: Rob Herring <robh@kernel.org>
>>>  ---
>>>   MAINTAINERS                                   | 10 +++
>>>   .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>>>   .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>>>   .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>>>   .../clock/mediatek,mt6735-topckgen.h          | 79 
>>> +++++++++++++++++++
>>>   5 files changed, 167 insertions(+)
>>
>> You should squash it with other part of binding. What is the reason
>> behind splitting one binding into three patches?
> 
> It seemed logical to me that each of clock and reset bindings as well 
> as documentation would be separate parts especially since they go in 

I don't understand. All of these are bindings. What do you mean by
"documentation"?

> different paths, but if combining them is how it's done then sure, I'll 
> squash them and resend.

They cannot go different paths and your submissions creates false
impression they can. If you want to see - apply these on separate
branches and test if: driver compiles and paths to files in doc are not
broken. Answer: driver won't compile and paths will point to
non-existing files.


Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
  2023-02-25 12:05   ` kernel test robot
  2023-02-27  8:19   ` Krzysztof Kozlowski
@ 2023-02-27  9:28   ` AngeloGioacchino Del Regno
  2023-02-27 10:39     ` Yassine Oudjana
  2 siblings, 1 reply; 15+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-27  9:28 UTC (permalink / raw)
  To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
	Michael Turquette, Stephen Boyd, Matthias Brugger, Philipp Zabel,
	Daniel Golle, Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai,
	Edward-JW Yang, Johnson Wang, Fabien Parent, Chun-Jie Chen,
	Miles Chen, Bartosz Golaszewski
  Cc: Yassine Oudjana, devicetree, linux-kernel, linux-clk,
	linux-mediatek, linux-arm-kernel

Il 25/02/23 10:42, Yassine Oudjana ha scritto:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
> clock and reset controllers. These provide the base clocks and resets
> on the platform, and should be enough to bring up all essential blocks
> including PWRAP, MSDC and peripherals (UART, I2C, SPI).
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
>   MAINTAINERS                                  |   4 +
>   drivers/clk/mediatek/Kconfig                 |   9 +
>   drivers/clk/mediatek/Makefile                |   1 +
>   drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++
>   drivers/clk/mediatek/clk-mt6735-infracfg.c   |  78 ++++
>   drivers/clk/mediatek/clk-mt6735-pericfg.c    |  91 ++++
>   drivers/clk/mediatek/clk-mt6735-topckgen.c   | 450 +++++++++++++++++++
>   7 files changed, 772 insertions(+)
>   create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
>   create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
>   create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
>   create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
> 

..snip..

> diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/mediatek/clk-mt6735-topckgen.c
> new file mode 100644
> index 000000000000..5fa743e4b0fc
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c
> @@ -0,0 +1,450 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
> +

..snip..

> +
> +int clk_mt6735_topckgen_probe(struct platform_device *pdev)

It gets *even easier* than that!

Check out this one:
https://patchwork.kernel.org/project/linux-mediatek/patch/20230222092543.19187-5-angelogioacchino.delregno@collabora.com/

...being part of:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=724004

So you can use simple_probe for MT6735's topckgen too!

In this case, it would be...

static const struct mtk_clk_desc topck_desc = {
	.clks = topckgen_muxes,
	.num_clks = ARRAY_SIZE(topckgen_muxes),
	.fixed_clks = topckgen_fixed_clks,
	.num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks),
	.factor_clks = topckgen_factors,
	.num_factor_clks = ARRAY_SIZE(topckgen_factors),
	.clk_lock = &mt6735_topckgen_lock,
};

static const struct of_device_id of_match_mt6735_topckgen[] = {
	{ .compatible = "mediatek,mt6735-topckgen", .data = &topck_desc },
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, of_match_mt6735_topckgen)
     ^^^^^
You're missing that on multiple clock drivers ;-)

...And you're replacing .probe(), .remove() callbacks with

static struct platform_driver clk_mt6735_topckgen = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,

	......

Other than that, good job!

After performing these changes, please make sure to mention the dependency on
my last cleanup series on your cover letter for v4, so that maintainers will
be aware of what to do.

Your v4 smells like Reviewed-by tags all over. Keep up the great work!

Cheers,
Angelo

^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-27  9:28   ` AngeloGioacchino Del Regno
@ 2023-02-27 10:39     ` Yassine Oudjana
  2023-02-27 12:42       ` AngeloGioacchino Del Regno
  0 siblings, 1 reply; 15+ messages in thread
From: Yassine Oudjana @ 2023-02-27 10:39 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno
  Cc: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel


On Mon, Feb 27 2023 at 10:28:06 AM +01:00:00, AngeloGioacchino Del 
Regno <angelogioacchino.delregno@collabora.com> wrote:
> Il 25/02/23 10:42, Yassine Oudjana ha scritto:
>> From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
>> clock and reset controllers. These provide the base clocks and resets
>> on the platform, and should be enough to bring up all essential 
>> blocks
>> including PWRAP, MSDC and peripherals (UART, I2C, SPI).
>> 
>> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>> ---
>>   MAINTAINERS                                  |   4 +
>>   drivers/clk/mediatek/Kconfig                 |   9 +
>>   drivers/clk/mediatek/Makefile                |   1 +
>>   drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++
>>   drivers/clk/mediatek/clk-mt6735-infracfg.c   |  78 ++++
>>   drivers/clk/mediatek/clk-mt6735-pericfg.c    |  91 ++++
>>   drivers/clk/mediatek/clk-mt6735-topckgen.c   | 450 
>> +++++++++++++++++++
>>   7 files changed, 772 insertions(+)
>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
>> 
> 
> ..snip..
> 
>> diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c 
>> b/drivers/clk/mediatek/clk-mt6735-topckgen.c
>> new file mode 100644
>> index 000000000000..5fa743e4b0fc
>> --- /dev/null
>> +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c
>> @@ -0,0 +1,450 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "clk-mtk.h"
>> +#include "clk-mux.h"
>> +
>> +#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
>> +
> 
> ..snip..
> 
>> +
>> +int clk_mt6735_topckgen_probe(struct platform_device *pdev)
> 
> It gets *even easier* than that!
> 
> Check out this one:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20230222092543.19187-5-angelogioacchino.delregno@collabora.com/
> 
> ...being part of:
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=724004
> 
> So you can use simple_probe for MT6735's topckgen too!

Isn't this basically what I did in v2[1][2]? What changed now?

> 
> In this case, it would be...
> 
> static const struct mtk_clk_desc topck_desc = {
> 	.clks = topckgen_muxes,
> 	.num_clks = ARRAY_SIZE(topckgen_muxes),
> 	.fixed_clks = topckgen_fixed_clks,
> 	.num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks),
> 	.factor_clks = topckgen_factors,
> 	.num_factor_clks = ARRAY_SIZE(topckgen_factors),
> 	.clk_lock = &mt6735_topckgen_lock,
> };
> 
> static const struct of_device_id of_match_mt6735_topckgen[] = {
> 	{ .compatible = "mediatek,mt6735-topckgen", .data = &topck_desc },
> 	{ /* sentinel */ }
> };
> 
> MODULE_DEVICE_TABLE(of, of_match_mt6735_topckgen)
>     ^^^^^
> You're missing that on multiple clock drivers ;-)
> 
> ...And you're replacing .probe(), .remove() callbacks with
> 
> static struct platform_driver clk_mt6735_topckgen = {
> 	.probe = mtk_clk_simple_probe,
> 	.remove = mtk_clk_simple_remove,
> 
> 	......
> 
> Other than that, good job!
> 
> After performing these changes, please make sure to mention the 
> dependency on
> my last cleanup series on your cover letter for v4, so that 
> maintainers will
> be aware of what to do.
> 
> Your v4 smells like Reviewed-by tags all over. Keep up the great work!
> 
> Cheers,
> Angelo

[1] 
https://lore.kernel.org/linux-mediatek/20220519142211.458336-5-y.oudjana@protonmail.com/
[2] 
https://patchwork.kernel.org/project/linux-clk/patch/20220519134728.456643-7-y.oudjana@protonmail.com/




^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
  2023-02-27 10:39     ` Yassine Oudjana
@ 2023-02-27 12:42       ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 15+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-27 12:42 UTC (permalink / raw)
  To: Yassine Oudjana
  Cc: Rob Herring, Krzysztof Kozlowski, Michael Turquette,
	Stephen Boyd, Matthias Brugger, Philipp Zabel, Daniel Golle,
	Allen-KH Cheng, Tinghan Shen, Chen-Yu Tsai, Edward-JW Yang,
	Johnson Wang, Fabien Parent, Chun-Jie Chen, Miles Chen,
	Bartosz Golaszewski, Yassine Oudjana, devicetree, linux-kernel,
	linux-clk, linux-mediatek, linux-arm-kernel

Il 27/02/23 11:39, Yassine Oudjana ha scritto:
> 
> On Mon, Feb 27 2023 at 10:28:06 AM +01:00:00, AngeloGioacchino Del Regno 
> <angelogioacchino.delregno@collabora.com> wrote:
>> Il 25/02/23 10:42, Yassine Oudjana ha scritto:
>>> From: Yassine Oudjana <y.oudjana@protonmail.com>
>>>
>>> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
>>> clock and reset controllers. These provide the base clocks and resets
>>> on the platform, and should be enough to bring up all essential blocks
>>> including PWRAP, MSDC and peripherals (UART, I2C, SPI).
>>>
>>> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>> ---
>>>   MAINTAINERS                                  |   4 +
>>>   drivers/clk/mediatek/Kconfig                 |   9 +
>>>   drivers/clk/mediatek/Makefile                |   1 +
>>>   drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++
>>>   drivers/clk/mediatek/clk-mt6735-infracfg.c   |  78 ++++
>>>   drivers/clk/mediatek/clk-mt6735-pericfg.c    |  91 ++++
>>>   drivers/clk/mediatek/clk-mt6735-topckgen.c   | 450 +++++++++++++++++++
>>>   7 files changed, 772 insertions(+)
>>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
>>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
>>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
>>>   create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
>>>
>>
>> ..snip..
>>
>>> diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c 
>>> b/drivers/clk/mediatek/clk-mt6735-topckgen.c
>>> new file mode 100644
>>> index 000000000000..5fa743e4b0fc
>>> --- /dev/null
>>> +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c
>>> @@ -0,0 +1,450 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/platform_device.h>
>>> +
>>> +#include "clk-mtk.h"
>>> +#include "clk-mux.h"
>>> +
>>> +#include <dt-bindings/clock/mediatek,mt6735-topckgen.h>
>>> +
>>
>> ..snip..
>>
>>> +
>>> +int clk_mt6735_topckgen_probe(struct platform_device *pdev)
>>
>> It gets *even easier* than that!
>>
>> Check out this one:
>> https://patchwork.kernel.org/project/linux-mediatek/patch/20230222092543.19187-5-angelogioacchino.delregno@collabora.com/
>>
>> ...being part of:
>> https://patchwork.kernel.org/project/linux-mediatek/list/?series=724004
>>
>> So you can use simple_probe for MT6735's topckgen too!
> 
> Isn't this basically what I did in v2[1][2]? What changed now?
> 

*Basically*, yes. *Practically*, no.

To answer all your questions about that, please read my part 1 series that already
landed. The part 2 adds the factor clocks to the mix and performs a full migration
to platform_driver and modularity to 99% of MediaTek clock drivers.

>>
>> In this case, it would be...
>>
>> static const struct mtk_clk_desc topck_desc = {
>>     .clks = topckgen_muxes,
>>     .num_clks = ARRAY_SIZE(topckgen_muxes),
>>     .fixed_clks = topckgen_fixed_clks,
>>     .num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks),
>>     .factor_clks = topckgen_factors,
>>     .num_factor_clks = ARRAY_SIZE(topckgen_factors),
>>     .clk_lock = &mt6735_topckgen_lock,
>> };
>>
>> static const struct of_device_id of_match_mt6735_topckgen[] = {
>>     { .compatible = "mediatek,mt6735-topckgen", .data = &topck_desc },
>>     { /* sentinel */ }
>> };
>>
>> MODULE_DEVICE_TABLE(of, of_match_mt6735_topckgen)
>>     ^^^^^
>> You're missing that on multiple clock drivers ;-)
>>
>> ...And you're replacing .probe(), .remove() callbacks with
>>
>> static struct platform_driver clk_mt6735_topckgen = {
>>     .probe = mtk_clk_simple_probe,
>>     .remove = mtk_clk_simple_remove,
>>
>>     ......
>>
>> Other than that, good job!
>>
>> After performing these changes, please make sure to mention the dependency on
>> my last cleanup series on your cover letter for v4, so that maintainers will
>> be aware of what to do.
>>
>> Your v4 smells like Reviewed-by tags all over. Keep up the great work!
>>
>> Cheers,
>> Angelo
> 
> [1] 
> https://lore.kernel.org/linux-mediatek/20220519142211.458336-5-y.oudjana@protonmail.com/
> [2] 
> https://patchwork.kernel.org/project/linux-clk/patch/20220519134728.456643-7-y.oudjana@protonmail.com/
> 
> 
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-02-27 12:42 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-25  9:42 [PATCH v3 0/4] MediaTek MT6735 main clock and reset drivers Yassine Oudjana
2023-02-25  9:42 ` [PATCH v3 1/4] dt-bindings: clock: Add MediaTek MT6735 clock bindings Yassine Oudjana
2023-02-27  8:18   ` Krzysztof Kozlowski
2023-02-27  8:29     ` Yassine Oudjana
2023-02-27  9:08       ` Krzysztof Kozlowski
2023-02-25  9:42 ` [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings Yassine Oudjana
2023-02-27  8:17   ` Krzysztof Kozlowski
2023-02-25  9:42 ` [PATCH v3 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2023-02-27  8:18   ` Krzysztof Kozlowski
2023-02-25  9:42 ` [PATCH v3 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers Yassine Oudjana
2023-02-25 12:05   ` kernel test robot
2023-02-27  8:19   ` Krzysztof Kozlowski
2023-02-27  9:28   ` AngeloGioacchino Del Regno
2023-02-27 10:39     ` Yassine Oudjana
2023-02-27 12:42       ` AngeloGioacchino Del Regno

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